DescriptionAs design process advancing, IR issues become more critical. If it happens in real silicon, it takes lots of time and effort to debug and solve, it also affect yield rate and time-to market. In order to reveal IR issues in pre silicon, we need to make sure IR signoff quality before tape out. However, there is no systematic method to qualify currently. We propose a metric, power-weighted toggle coverage, to do this. Our approach can score patterns using coverage concept without real power simulation. Experimental result shows high relationship between power coverage and IR result.