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MOVE TO VIRTUAL: LabReplay: Efficient Replay of Post-Silicon Debug for High Performance Microprocessor Designs
TimeMonday, December 6th5:00pm - 6:00pm PST
LocationLevel 2 - Exhibit Hall
Event Type
Designer, IP and Embedded Systems Track Poster Networking Reception
Virtual Programs
Presented In-Person
DescriptionIn the microprocessor design cycle, time spent in the hardware lab is crucial. There is a need to resolve issues seen in the hardware lab as quickly as possible. The data available from hardware is partial. Access to more expanded data based on this partial hardware dump data helps lab debug significantly. Design flows using a step-wise refinement implementation present new opportunities to perform hardware debug in the simplified design intent (NMZ) model of hardware. We introduce LabReplay, the first such post-silicon debug flow, to create “expanded” hardware debug data set in the “simpler” NMZ model. Compared to current state of art techniques, LabReplay uniquely brings together 3 key aspects: 1) "Shift right” the principle of Designer Level Verification 2) Perform “replay” on the simpler NMZ model of hardware 3) And the new application of X-state simulation. Experimental evaluation of LabReplay on industry-class next-generation high-performance microprocessor designs, like the IBM POWER10, demonstrate the efficiency of the approach. We believe the techniques described are generic and advocate the application of these techniques to complement existing post-silicon hardware lab debug.