DescriptionSplitting of large SOC into chiplets within package requires chip-2-chip (C2C) communication interfaces. This presentation lists the C2C PHY design goals, challenges in energy efficiency improvement, and design strategies. Bunch of wires standard targets data rates of 1-16Gb/s and extremely short lengths up to 10mm. While CEI56G-XSR-NRZ supports lengths up to 50mm and data rates up to 58Gb/s. Minimizing the driven signal voltage swing is the critical strategy in reducing the power. The minimum voltage swing is dependent upon the noise due to crosstalk, power supply noise, impedance mismatch and equalization requirements. The biggest factor is the equalization which is much less in XSR C2C interfaces. If receiver offset/sensitivity are good enough, even voltage swings at receiver of 50mV could be used with transmitted swing of only 100mV due to 6dB (0.5x) equalization. A 13Gb/s source series terminated voltage mode transmitter which fits under a single pad of 60µm. Newer technologies further reduce the pad size which shall further limit the decoupling capacitance placement and the voltage swing. Reducing crosstalk, power supply noise, 6dB Transmitter FFE, Receiver CTLE equalization and low receiver offset and high sensitivity allow voltage swing, VDD to be reduced tremendously and improved pJ/bit energy efficiency.