Verifying Reset and Power Domains Together
TimeTuesday, December 7th5:00pm - 6:00pm PST
Event Type
Designer, IP and Embedded Systems Track Poster Networking Reception
Virtual Programs
In-Person Only
DescriptionThe Unified Power format (UPF) standard enables designers to add power intent for the design. For power management designers typically partition design into power domains. Interactions between these power domains are done through various power control logics like retention logic, isolation logic, level shifters, etc.
Designers need to validate that the power control logic does not introduce new multi-clock and multi-reset issues into the design. This paper specifically talks about the issues encountered in Reset Domain Crossing introduced by UPF instrumentation. UPF instrumentation may lead to higher number of new Resets which are not part of the design specification leading to huge verification turnaround time.
This paper also explores the possibilities of enhancing the features of a static verification tool by proposing new rule-sets for the tool.