DescriptionThe access path used for communication within SOC is categorized into two types -Configuration path and data path, configuration path is exercised with Non-Coherent(NC) transactions whereas Coherent transactions are used to access the data path. With the growing SOC complexity, the NOC(Network on-chip) stitching the components is getting complicated hence leading to complex access paths. Infrastructure exists to validate coherent transactions, which are scoped around different memory hierarchies, and hence a standard set of stimuli and assertions are enough to validate such transactions. On the contrary, the NC transactions have a wider scope which encompasses both memory and peripheral transactions. Such NC transactions involve the configuration of a range of registers at the SOC. The validation infrastructure simply succumbs when such NC access is exploited around SOC involving thousands of registers. Solutions do exist which involve RAL-based NC register validation, but this methodology is fraught with limitations and can only validate a few hundred registers in a limited simulation time span but not the functionality. We propose a novel robust NC access validation mechanism that is viable across platforms i.e. simulation and emulation and can exploit/access all the registers to validate different NC functional scenarios with auto coverage/test stimulus generation.