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Get more out of your UVM register Layer!
Time
Location
Event Type
Designer, IP and Embedded Systems Track Presentations
Virtual Programs
Hosted in Virtual Platform
Topics
Front-End Design
DescriptionVerification Engineers using UVM for functional verification, are typically adopting the UVM Register abstraction layer(RAL) too, for modeling registers in their test benches(TB). Adopting RAL provides various benefits
1) Test writer need not be aware of either the physical address of the register in the Design under test (DUT), or the protocol used for register access.
2) Easier test case maintenance and portability( because of the protocol agnostic register access).
3)Modeling the current configuration state of DUT in the TB, helps in creating better reference models and scoreboards.

UVM documentation doesn’t do a good job of explaining advanced RAL constructs and their implications, hence a typical user limits his usage to basic APIs ‘read’, ’write’, ‘predict’, ‘set’, ‘mirror’ etc.. This paper attempts to explain advanced RAL concepts like register callbacks, bus extensions, method hooks and user defined front door sequences.
We explain use cases for these constructs (and their combination) and explain how to model complex register behaviors like burst accesses, quirky registers, secure registers, register side effects, non-linear addressing etc.