DescriptionFor maximizing the performance of a SOC (System on Chip), it is important to reduce the thermal coupling among heat sources in a design by evenly distributing heat sources. The location of heat sources is decided in a floorplanning stage, so floorplanning needs to be done in a thermal-aware way. However, previous thermal-aware floorplanning methods relied on resource/time-consuming empirical methods, which makes it hard for such methods to be used for large designs. In this work, we propose a thermal-aware floorplanning method based on a DQN (Deep-Q Network) algorithm. The method uses a DQN for a fast temperature calculation for a heat source (i.e. SOC block), and it can be expanded to multiple heat sources using superposition. Thanks to the fast temperature calculation engine, the proposed method can quickly decide the best block placement that results in the lowest maximum temperature of a given design.