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On-Chip Dynamic IR Drop Induced Deterministic Jitter Analysis
Time
Location
Event Type
Designer, IP and Embedded Systems Track Presentations
Virtual Programs
Hosted in Virtual Platform
Topics
Back-End Design
DescriptionThe unified on-chip level power supply noise induced jitter analysis method is presented. The dynamic voltage drop simulation using vectorless scenario is performed. Cycle based spice deck files to analyze jitter are generated from static timing analysis session by reading dynamic voltage drop data to consider impact of power supply noise fluctuation. SPICE-based simulations were executed to get jitter values with over 75 cycles. The proposed method is integrated with dynamic voltage drop analysis, spice deck file extraction, and spice-based jitter calculation in a single flow. Results show that simulation time for 1358 paths with over 75 cycles is 81 hours, 56 hours for dynamic voltage drop analysis and 25 hours for spice deck generation and spice simulation, and its jitter values are less than 25ps for all paths.