Routing layer re-optimization in Physical Synthesis
TimeMonday, December 6th1:50pm - 2:10pm PST
Event Type
Designer, IP and Embedded Systems Track Presentations
Virtual Programs
Presented In-Person
Back-End Design
DescriptionPhysical Synthesis tools typically use heuristic optimization techniques to cope with ever increasing design sizes. They also need to deal with optimizing multiple objectives such as improving timing, decreasing area/power, reducing congestion, and so on. In addition, the accuracy of optimization environment varies as we go through the Physical Synthesis flow. All these factors may lead to sub-optimal thick metal layer assignments and inferior timing QOR on some timing critical nets. We propose a novel routing layer re-optimization technique that attempts to (re)assign thick metal routing resource with the goal of significantly mitigating routing congestion as well as improving design timing QOR.
The proposed technique starts with an aggressive layer demotion (during late timing optimization stages) in the routing congested regions even at the expense of timing QOR to provide an opportunity to correct/improve layer assignment. The timing QOR recovery/improvement phase follows next, initially with cheaper optimizations to reduce the need for precious routing layer resource as well as to correct any underlying issues such as sub-optimal locations / weak power levels. Next, we perform a gradual & controlled layer reassignment / buffering in a congestion-aware environment to mitigate congestion increases while improving timing QOR.