Clocking Methods with Focus on PCIe Gen4
TimeWednesday, December 8th10:50am - 11:10am PST
Event Type
Designer, IP and Embedded Systems Track Presentations
Virtual Programs
Presented In-Person
Back-End Design
DescriptionGood clock latency and skew can be hard to attain on complex IP when using default settings. Difficulties during clock build with PCIe Gen4 with a certain vendor has been strenuous and time-consuming. In this design, the clock and design are overly complex with multiple IP configurations and over 36 clocks. The four methods developed are regioning PCIe logic, analyzing the skew groups, inserting a h-tree, and refraining certain clocks to be balanced. The methods improved turnaround time, clock skew, and clock latency; therefore, attaining an acceptable clock tree in a reasonable time frame and enabling successful tapeouts on multiple projects.