Joo-Young Kim (Senior Member, IEEE) received the B.S., M.S., and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea, in 2005, 2007, and 2010, respectively. He was one of the initial members of the Catapult project at Microsoft Research, Redmond, WA, USA, where he deployed a fabric of field-programmable gate arrays (FPGAs) in datacenters to accelerate critical cloud services, such as machine learning, data storage, and networking. He was a Senior Hardware Engineering Lead at Microsoft Azure, Redmond, WA, USA, working on hardware acceleration for its hyper-scale big data analytics platform named Azure Data Lake. He has been an Assistant Professor with the School of Electrical Engineering, KAIST, since September 2019. His research interests span various aspects of hardware design, including VLSI design, computer architecture, FPGA, domain-specific accelerators, hardware/software codesign, and agile hardware development. Dr. Kim was a recipient of the 2016 IEEE Micro Top Picks Award, the 2014 IEEE Micro Top Picks Award, the 2010 DAC/ISSCC Student Design Contest Award, the 2008 DAC/ISSCC Student Design Contest Award, and the 2006 A-SSCC Student Design Contest Award. He serves as an Associate Editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS for the term 2020–2021.