Neil More VLSI Design Engineer and researcher at Silicon Interfaces is skilled in verification techniques for portability, coverage automation, and fault simulations and languages, like Domain Specific Language (DSL) and methodologies, like UVM as well as SystemVerilog as well as work on test realization of single intent verification across platforms. Recently, has been active in several projects to increase coverage goals for PCIe and AXI/CHI interfaces.
Designer, IP and Embedded Systems Track Poster Networking Reception
Presented In-Person