Yun(Eric) Liang is currently an Associate Professor (with tenure) with the School of Electrical Engineering and Computer Science, Peking University. His research focuses on heterogeneous computing (GPUs, FPGAs, ASICs) for emerging applications such as AI and big data, computer architecture, compilation techniques, programming model and program analysis, and embedded system design. He has authored more than 80 scientific publications in premier international journals and conferences in related domains. His research has been recognized by best paper award at FCCM 2011 and ICCAD 2017 and best paper nominations at PPoPP 2019, DAC 2017, ASPDAC 2016, DAC 2012, FPT 2011, CODES+ISSS 2008. He serves as an Associate Editor for the ACM Transactions in Embedded Computing Systems and Embedded System Letters, and serves in the program committees in the premier conferences in the related domain including (HPCA, MICRO, DAC, ASPLOS, PACT, PPoPP, CGO, ICCAD, ICS, FPGA, FCCM). He is the corresponding author of this article. Contact him at firstname.lastname@example.org.
RTL/Logic Level and High-level Synthesis
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