Satish has been working in the area of Logic Equivalence Methodology for the past 15+ years in both Formal and Dynamic areas. His contributions to both methodology and execution aspects on multiple generations of Giga-Scale SOCs have helped achieve Power-On worthy Silicon quality. His innovative approaches have helped bridge many sign-off gaps that are either tool short comings or execution blind-spots. This poster describes his work on Hybrid GLS Simulation methodology that overcomes cost, scalability and predictability issues over traditional GLS approaches in Giga-Scale SOCs.
Designer, IP and Embedded Systems Track Poster Networking Reception