I'm a principle engineer for Samsung electronic S.LSI business, where I'm working to develop timing sign-off methodology including regular sign-off and robust deisgn sign-off flows of advanced process nodes. My main area is developing value-added flows and analyzing silicon based on the STA timing. Also, I've worked for over 10 years in CPU/GPU hardening field and my main role was netlist generation using synthesis tool and low power optimiztion and ECO for timign closure.
Designer, IP and Embedded Systems Track Presentations
Presented In-Person