Xiao Bin has a long history of complex chip and system design at companies including Sanechips, Texas Instruments. He worked on leading technology development, advanced power optimization and analysis, and signal integrity design methodologies for Sanechips's successful wireless base station and network products. He has a deep understanding of ASIC backend designs , including chip floorplan, STA timing and IR Drop analysis with over 30 successful chip tapeouts. He has also been responsible for system architecture of low power implementation, including power states definition, power saving technique, and energy efficiency improvement.
Advanced chip designs have many components, including muti-core architecture, high frequency peripherals and hardware accelerators. These design elements require a more accurate pathway to analysis the power and signal intergrity for safety and reliability concerns. Xiao Bin has put more efforts to mitigate the challenges associated with power integrity characterization and simulation.
Designer, IP and Embedded Systems Track Poster Networking Reception