Shivani Pandya is a Senior Engineer with Marvell in the Santa Clara ASIC Design Center and has been responsible for Physical Design in various technologies for the past 3 years. Shivani has assisted in taping out a 14 nm design and has worked on multiple projects and helped with benchmarking technologies ranging from 5 to 7nm. As a PD engineer, Shivani has closed timing critical blocks by leveraging the tool capabilities and is currently working on a 7nm Marvell offering. Shivani holds a Master of Technology in VLSI and Embedded systems from Ganpat University.
Designer, IP and Embedded Systems Track Poster Networking Reception