Tuo Li is a postdoctoral researcher with the School of Computer Science and Engineering, University of New South Wales. His current research interests include timing channel mitigation, memory safety, and fault tolerance in computer architecture. He received a Ph.D. degree in computer science and engineering from the University of New South Wales, Sydney, Australia, in 2014. He has been a reviewer for various journals such as IEEE TCAD, IEEE Access, IET Computers & Digital Techniques, IEEE TVLSI, IEEE TDSC, IEEE Embedded System Letters, JETC. He also has served as a reviewer for security, hardware, and embedded system conferences such as CCS, DAC, ICCAD, DATE, ESWEEK, ASP-DAC, VLSID, RTAS, RTSS.
Embedded and Cross-Layer Security
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