As experienced chip design methodology developer and manager, Naya Ha has worked across multiple foundry ecosystem disciplines in both EDA and Cloud, and built and strengthened the alliance for customer success. Ha joined Samsung Electronics in 2005 and was involved in the development of design for manufacturability techniques and novel static timing methodologies for advanced node technologies aspects of interconnect modeling, model to hardware correlation, and uncertainty margining. Her current focus is in solving customer challenges, including to expand chip design footprint to cloud regions. She received a B.S. and M.S. from Hanyang University, Seoul, Korea.
Designer, IP and Embedded Systems Track Poster Networking Reception