Dipto Thakurta, Sr. Principal Engineer, Design Enablement, Intel
Dipto joined Intel in 2001 after completing his Ph.D. from Rensselaer Polytechnic Institute, New York. He leads Intel’s Technology Development Test-chip design, execution, and technical innovation of all the targeted process learning vehicles. He specializes in testchip design for yield and parametric learning for various stages of process maturity starting from pathfinding through end of development. He has expertise in designing quick turn monitors for defect specific accelerated yield learning. He has led several innovative testchip design solutions across technology nodes including the development of short loop vehicles, the implementation of product-like back-end layouts for test early in the development cycle, and development of optical voltage contrast structures for high volume yield monitoring and process margin learning across a variety of defect modes. Prior to leading the testchip design team Dipto worked on process modelling in TCAD, OPC synthesis flows and layout classification and analytics for yield improvement, and in design rule definition and runset development.
Designer, IP and Embedded Systems Track Poster Networking Reception