Sidharth Ranjan Panda is an Engineering Manager with ~ 9years of working experience in the field of Backend Formal verification and functional ECO closure across designs. Currently he is responsible for formal equivalence verification execution and signoff activities, Low Power verification execution and signoff activities, functional ECOs closure in design cycle for all products in HSPE Business Unit at Intel.
He holds M.Tech Degree in Microelectronics Domain from BITS Pilani, India.
Designer, IP and Embedded Systems Track Presentations
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