Walter Lau received the B.Sc. degree in Computer Engineering from Pontifícia Universidade Católica do Rio Grande do Sul (PUCRS) in 2017, the M.Sc. degree in Microelectronics from Universidade Federal do Rio Grande do Sul (UFRGS) in 2018, both in Porto Alegre, Brazil. He is currently pursuing a Ph.D. in Computer Engineering at the University of Utah.
His research interests include digital circuit design, electronic design automation (EDA), logic synthesis and asynchronous circuits.
RTL/Logic Level and High-level Synthesis
Special Session (Research Track)
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