Abhinav Parashar joined TI in July 2017 as Design Verification Engineer in Simplelink division of Connected MCU, now Connectivity Group. He has done hands on front-end activities like RTL Lint, CDC, Power Estimation and Synthesis along with IP and SoC Verification using simulation and formal approach. He is actively involved discussions with Cadence for RTL Lint and CDC analysis and verification aspects. He has good experience in IP and SoC verification and currently involved in the verification of connectivity class of devices. He has come up with multiple Formal Verification methodologies. He has authored 9 papers in conferences like TIITC, DAC, VLSID, CDN Live, IEEE Wintechcon and has delivered a tutorial on Formal Verification in Digital and Mixed Signal Designs in TIITC, a TI internal international conference.
Designer, IP and Embedded Systems Track Poster Networking Reception