Close

Presenter

Biography
1996, 3 ~ 2003, 2 : B.S. in Computer Engineering Dept., Sogang University, Seoul, Korea
2003, 3 ~ 2005, 2 : M.S. in VLSI/CAD, Sogang University, Seoul, Korea
2014, 3 ~ 2018, 8 : Ph.D. in Department of Semiconductor Systems Engineering , SKKU Sungkyunkwan University, Suwon, Korea
2005, 3 ~ 2014, 2 : Process Aware Timing Sing-off design methodology, Development of Process monitoring IP or Test Chip
2017, 2 ~ 2018, 4 : 7LPP/5LPP DTCO (Design Technology Co-Optimization)
2018,4 ~ : Adaptive design technique (CL-DVFS, Droop Mitigation)
Presentations
Designer, IP and Embedded Systems Track Presentations
Front-End Design
Hosted in Virtual Platform