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My Agenda

Organizations

A*STAR Institute of High Performance Computing

Academia Sinica

Achronix

Advanced Digital Sciences Centre (ADSC)

Airbus Defence and Space

Argonne National Laboratory

Arizona State University

Arm Ltd.

Arrikto, Metrics, Kwikbit

Association of HPC Pros

Beijing Institute of Control Engineering

Beijing University of Posts and Telecommunications

Blue Cheetah Analog Design

Boston Children's Hospital

Boston University

Breker Verification Systems

British Columbia Academy

Brno University of Technology

Brown University

Cadence Design Systems, Inc.

Cairo University

Capital Normal University

CEA

CEA LIST

Central South University

Cerebras

Charles University

China Academy of Space Technology

China University of Petroleum

Chinese Academy of Sciences

Chinese University of Hong Kong

CHIPS Alliance

Chronos Tech

City University of Hong Kong

City University of London

CMC Microsystems

CNRS

Codasip

Codeplay Software Ltd.

College of Information Science and Engineering

College of William and Mary

Colorado State University

Columbia University

Comark

Computational Science & Engineering Team

Daegu Gyeongbuk Institute of Science and Technology

Dalhousie University

DARPA

Dell EMC

Design Technology Team

DFKI GmbH

DGIST

Digital Design Group

Digital Security Group, Radboud University

East China Normal University

Edgecortix Inc

EECS, National Tsing Hua University,

EETimes

Electrical & Computer Engineering

Farroupilha Federal Institute

Federal University of Pampa

Federal University of Rio Grande do Sul

Florida International University

FortifyIQ

Forza Silicon (Ametek Inc.)

FOSSI Foundation

Fraunhofer IIS/EAS

Fraunhofer Institute for Applied and Integrated Security (AISEC)

Fraunhofer Institute for Cognitive Systems IKS

Fraunhofer Institute for Integrated Circuits IIS Division Engineering of Adaptive Systems EAS

Fraunhofer USA

Fudan University

Fuzhou University

General Dynamics Mission Systems

George Mason University

George Washington University

Georgia Institute of Technology

Georgia Tech Research Institute

Global Unichip Corp.

Google

Google LLC

Graduate Institute of Electronics Engineering, National Taiwan University

Griffin Securities

Guangdong General Hospital

Guangdong Provincial People's Hospital

Guangdong University of Technology

Hanyang University

Harvard University

Haute Ecole d'Ingénierie et de Gestion du Canton de Vaud

Hefei Reliance Memory Ltd.

Hewlett Packard Enterprise

Hong Kong University of Science and Technology

HP-NTU Digital Manufacturing Corporate Lab, Nanyang Technological University

Huada Empyrean Software Co., Ltd

Huawei

Huawei Technologies Company Ltd.

Huawei Technologies Company, Ltd.

Huazhong University of Science and Technology

IBM Systems Chip Design

IBM Thomas J. Watson Research Center

Imperas Software Ltd.

Imperial College London

Independent

Indian Institute of Science

Indian Institute of Technology Goa

Indian Institute of Technology Kharagpur

Infineon Technologies AG

Innovations and Experiences – Business Personal Systems, HP Inc.

Institute for Infocomm Research

Institute of Computing Technology, Chinese Academy of Sciences

Instituto de Telecomunicações

Instituto Superior Técnico – Universidade de Lisboa

Intel

Intel Corporation

Intel Labs

Intel Technology India Pvt. Ltd.

Intento Design

Iowa State University

ITRenew

Johannes Kepler University

Johannes Kepler University Linz

Kansas State University

Karlsruhe Institute of Technology

Kastner Lab

KIOS Research and Innovation Center of Excellence

Kobe University

Korea Advanced Institute of Science and Technology (KAIST)

Lawrence Berkeley National Lab

Lawrence Technological University

Lehigh University

Leibniz Universität Hannover

Leiden University

Leiden University and KU Leuven

LightBug

Logarithm Labs

Marvell Semiconductor

Massachusetts Institute of Technology

Michigan Technological University

Micron

Microsoft

Microsoft Azure

Microsoft Corporation

Mirabilis Design Inc.

Nagoya University

Nanjing Foreign Language School

Nanjing University

Nanjing University of Aeronautics and Astronautics

Nanjing University of Science and Technology

Nanyang Technological University

National Central University

National Chiao Tung University

National Taipei University of Technology

National Taiwan University

National Technical University of Athens

National Tsing Hua University

National University of Sciences and Technology

National University of Singapore

Nereus

New York University

New York University Abu Dhabi

New York University, Abu Dhabi

NJIT

North Carolina State University

North Dakota State University

Northeastern University

Northrop Grumman

Northwestern University

Notre Dame

NTT

NTT Basic Research Laboratories

NTT Data

NTT Nanophotonics Center

NVIDIA

NXP Semiconductors Inc.

NYU

NYU Abu Dhabi

Oak Ridge National Laboratory

Ohio University

Oklahoma State University

Pacific Northwest National Laboratory

Paradigm Works

PCI-SIG

Peking University

Penn State College of Medicine

Pennsylvania State University

PerceptIn

perforce

Plunify

Politecnico di Milano

Politecnico di Torino

Raytheon Technologies Research Center

Real Intent Inc

Reconova Technologies

Renesas Electronics Corporation

San Francisco State University

Sandia National Labs

Sanechips Technology Co., Ltd

Sanechips Technology Co.,Ltd

School of Computer Science and Engineering, Nanyang Technological University

School of Computer Science and Technology, East China Normal University, Shanghai, China

School of Computer Science and Technology, University of Science and Technology of China

School of Computing, National University of Singapore

School of Software Engineering, University of Science and Technology of China

Scuola Superiore Sant'Anna

Secure-IC

Semi Engineering

Semiconductor Engineering

Seoul National University

Shandong University

Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences

Shanghai Jiao Tong University

ShanghaiTech University

Silicon Integration Initiative, Inc.

Silicon Interfaces

Silvaco

Simon Fraser University

Singular Medical Co., Ltd.

SKLCA, Institute of Computing Technology, Chinese Academy of Sciences

Software/Hardware Co-design Engineering Research Center, Ministry of Education

Sookmyung Woman's University

Soongsil University

South China University of Technology

Southeast University

Southern Illinois University

Southern University of Science and Technology

Spillbox

Stanford University

State Key Laboratory of Computer Architecture

State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences

State Key Laboratory of Mobile Network and Mobile Multimedia Technology

Stevens Institute of Technology

STMicroelectronics

Sun Yat-Sen University

Sungkyunkwan University

Suzhou Research Institute, University of Science and Technology of China

Swiss Federal Institute of Technology, Lausanne (EPFL)

Synopsys

Syracuse University

System LSI Business

Tactical Computing Laboratories

Tamkang University

Tata Consultancy Services Ltd.

Technical University of Darmstadt

Technical University of Munich

Technion - Israel Institute of Technology

Technion, Israel Institute of Technology

Technische Universität Darmstadt

Technische Universität Kaiserslautern

Technische Universität Wien

Tendung Technology

Texas A&M University

Texas A&M University at Corpus Christi

Texas Instruments

Texas Instruments (India) Pvt. Ltd.

Texas State University

The Chinese University of Hong Kong

The Hong Kong Polytechnic University

The University of Texas at Austin

The University of Texas at Dallas

The University of Texas at San Antonio

The University of Tokyo

TU Darmstadt, Purdue University

Universidad Nacional Autónoma de México

Università degli Studi dell'Aquila

Università della Svizzera italiana

Universität zu Lübeck

Université Grenoble Alpes

Université Polytechnique Hauts-De-France

University College London

University of Birmingham

University of Bologna

University of Bremen

University of Calgary

University of California, Berkeley

University of California, Davis

University of California, Irvine

University of California, Los Angeles

University of California, Riverside

University of California, San Diego

University of California, Santa Barbara

University of California, Santa Clara

University of Cambridge

University of Central Florida

University of Chinese Academy of Sciences

University of Connecticut

University of Cyprus

University of Edinburgh

University of Electronic Science and Technology of China

University of Florida

University of Glasgow

University of Illinois

University of Illinois at Chicago

University of Illinois at Urbana-Champaign

University of Louisiana

University of Maryland

University of Maryland, Baltimore County

University of Michigan

University of Minnesota

University of Nebraska - Lincoln

University of New Mexico

University of New South Wales

University of Notre Dame

University of Nottingham Ningbo, China

University of Pennsylvania

University of Pittsburgh

University of Rochester

University of Saarland

University of Science and Technology of China

University of South Alabama

University of South Carolina

University of Southampton

University of Southern California

University of Stuttgart

University of Technology Sydney

University of Tennessee Knoxville

University of Texas at Dallas

University of Thessaly

University of Tokyo

University of Utah

University of Verona

University of Washington

University of Waterloo

University of Wisconsin-Madison

University of York

University Politehnica of Bucharest

USI Lugano

Utah State University

Veriest Solutions Ltd.

VerifAI Inc.

Verilab

Vienna University of Technology

Villanova University

Virginia Commonwealth University

Virginia Polytechnic Institute and State University

Vrĳe Universiteit Brussel (VUB)

Vrije Universiteit Brussel (VUB)

Wabtec

Washington State University

Washington University in St.Louis

Wayne State University

Western Digital

Wistron NeWeb Corporation

Worcester Polytechnic Institute

Xi'an Jiaotong University

Session Chair(s)

Kholoud Mahmoud Ahmed

Mohammad Abdullah Al Faruque

Iraklis Anagnostopoulos

Lakshmanan Balasubramanian

Antonio Carlos S. Beck

Zineb Benameur-El Youbi

Dhritiman Bhattacharya

Jeffrey Brownscheidle

Benjamin Carrion Schaefer

Vito Giovanni Castellana

Krishnendu Chakrabarty

Maheshwar Chandrasekar

Thidapat (Tam) Chantem

Muhammad waqas Chaudhary

Jovanka Ciric Vujkovic

Ivan De Oliveira Nunes

Keerthikumara Devarajegowda

Sai Manoj Pudukotai Dinakarrao

Anna Lena Duque Antón

Alexander James Edwards

Juan Fernando Eusse Giraldo

Mohammad Farhadi Bajestani

Massimo Franceschetti

Pierre-Emmanuel Gaillardon

Krishnakanth Gilakamsetti

Kailash Gopalakrishnan

Padmini Gopalakrishnan

Muhammad Abdullah Hanif

Mohsen Hassanpourghadi

Antti E. J. Hyvärinen

Alejandro Hérnandez Cano

Mohammad Majharul Islam

Daniele Jahier Pagliari

Ashish Jaitly

Sashidhar Jakkamsetti

Vijay Janapa Reddi

Rajesh Jayaprakash

Jean-Baptiste Jeannin

Jie-Hong Roland Jiang

Chandramouli V. Kashyap

Raees Kizhakkumkara Muhamad

Venkataraghavan Krishnan

Anton Kryukov

Sumit Kumar Kulshreshtha

Abraham Peedikayil Kuruvila

Vladimir Litovtchenko

Arthur Francisco Lorenzon

Chayapol Lortararparset

Marcelo Caggiani Luizelli

Sandro Matheus Marques

Thiarles Soares Medeiros

Roshanak Mohammadivojdan

Luis Gabriel Murillo Gomez

Srinarayana Nagarathinam

Santosh Mahadeo Narawade

Michael F. P. O'Boyle

George - Ioannis Paliaroutis

Sidharth Ranjan Panda

Ganapathy Parthasarathy

Sai Surya Kiran Pentapati

Sebastian Siegfried Prebeck

Rachmad Vidya Wicaksana Putra

Rudy Raymond Harry Putra

Jonathan Ragan-Kelley

Mohammad Rahmani Fadiheh

Balachandran Rajendran

Jeyavijayan Rajendran

Satish Kumar Rompicharla

Md Sami Ul Islam Sami

Alberto Sangiovanni-Vincentelli

VIJAYKUMAR SANKARAN

Marco D. Santambrogio

Rahul Santhosh Kumar Varma

Mustafa Munawar Shihab

Myung Seok Shim

Sung Hoon (Ryan) Shim

Nima Shoghi Ghalehshahi

Mohammad Abdullah Al Shohel

Paul Peter Sotiriadis

Ourania Spantidi

Leo Sporn

Ravishankar Sreedharan

Vaidyanathan Srinivasan

Vinayakam Subramanian

Karthik Somayaji Suryanarayana

Michael Bedford Taylor

Theocharis Theocharides

Matheus Trevisan Moreira

Jasper van Woudenberg

Gaurav Kumar Varshney

Rangharajan Venkatesan

Jackson Cunningham Woodruff

Presentations

Designer, IP and Embedded Systems Track Poster Networking Reception

"OpenOPU" , A Complete Solution for Heterogeneous Computing

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

“Debug in/on/with the Virtual Platform” – Please Clarify!

Embedded Systems

Hosted in Virtual Platform

Research Manuscript

3D-Adv: Black-Box Physical Adversarial Attacks against Deep Learning Models through 3D Sensors

Security

Hardware Security: Attack and Defense

Presented In-Person

Research Manuscript

A Bridge-based Compression Algorithm for Topological Quantum Circuits

Design

Quantum Computing

Hosted in Virtual Platform

Research Manuscript

A Charge-Sharing based 8T SRAM In-Memory Computing for Edge DNN Acceleration

Design

AI/ML System Design

Hosted in Virtual Platform

Research Manuscript

A Complete PCB Routing Methodology with Concurrent Hierarchical Routing

EDA

Physical Design and Verification, Lithography and DFM

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Presentations

A comprehensive UPF coverage methodology to avoid late Si Issues

Front-End Design

Hosted in Virtual Platform

Research Manuscript

A Compute-in-Memory Architecture Compatible with 3D NAND Flash that Parallelly Activates Multi-Layers

Embedded Systems

Near-Memory and In-Memory Computing

Hosted in Virtual Platform

Networking Reception

Work-in-Progress Poster

A Coordinated GPU Overdrive Fault Attack on Neural Networks

Presented In-Person

Research Manuscript

A Finer-Grained Blocking Analysis for Parallel Real-Time Tasks with Spin-Locks

Embedded Systems

Time-Critical System Design

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Presentations

A flexible SAR-ADC IP for multiple technodes

Presented In-Person

Research Manuscript

A Formal Approach to Confidentiality Verification in SoCs at the Register Transfer Level

Security

Embedded and Cross-Layer Security

Presented In-Person

Research Manuscript

A Framework for Optimizing CPU-iGPU Communication on Embedded Platforms

Embedded Systems

Embedded Software

Hosted in Virtual Platform

Networking Reception

Work-in-Progress Poster

A High Efficiency Power Obfuscation Switched Capacitor DC-DC Converter Architecture

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

A Highly Reusable Generic UVM for Soft Processors

Presented In-Person

Research Manuscript

A Lightweight Isolation Mechanism for Secure Branch Predictors

Security

Hardware Security: Primitives, Architecture, Design & Test

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Presentations

A Low Cost, Scalable and Predictable Gate Level Simulation Methodology for Giga-Scale SOCs

Presented In-Person

Research Manuscript

A New, Computationally Efficient “Blech Criterion” for Immortality in General Interconnects

EDA

Manufacturing Test and Reliability

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

A Novel Clock Gating Design and Verification Methodology to Ensure Safe Power Optimization

Front-End Design

Hosted in Virtual Platform

Research Manuscript

A Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large Designs

EDA

Digital Design, Timing and Simulation

Hosted in Virtual Platform

Research Manuscript

A Resource Binding Approach to Logic Obfuscation*

Security

Hardware Security: Primitives, Architecture, Design & Test

Presented In-Person

Networking Reception

Work-in-Progress Poster

A Robust DNN Accelerator with Data-path Fault Detection and Mitigation

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

A Scalable Multicore RISC-V GPGPU Accelerator for High-End FPGAs

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

A Spring Model Approach For Timing Budget Apportionment

Presented In-Person

Research Manuscript

A Two-Stage Neural Network Classifier for Data Imbalanced Problem with Application to Hotspot Detection

EDA

Physical Design and Verification, Lithography and DFM

Presented In-Person

Research Manuscript

A Unified DNN Weight Pruning Framework Using Reweighted Optimization Methods

Design

Approximate Computing for AI/ML

Hosted in Virtual Platform

Research Manuscript

A3C-S: Automated Agent Accelerator Co-Search towards Efficient Deep Reinforcement Learning

Design

AI/ML System Design

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Abstraction- An efficient methodology for RTL & Low-Power Signoff in SoC Design

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

Accelerating advanced node ramp up and robust Design Enablement for leading edge SoC designers

Presented In-Person

Special Session (Research Track)

Accelerating Fully Homomorphic Encryption with Processing in Memory

Design

Security

Hosted in Virtual Platform

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Accelerating mutation coverage measurement by using concurrent fault simulator

Front-End Design

Hosted in Virtual Platform

Special Session (Research Track)

Accelerating PCB Layout Editor using modern GPU architecture for complex designs

EDA

Machine Learning/AI

Hosted in Virtual Platform

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

Accelerating Standard Cells Variation-Aware Characterization Methodology with Machine Learning Techniques

Presented In-Person

SKY Talk

Accelerator Architectures and Machine Learning

Hosted in Virtual Platform

Presented In-Person

Lunch and Learn

Accellera Luncheon

Design

EDA

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

Accurate and efficient high-performance memory modeling for full-chip power noise analysis

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Accurate glitch noise analysis considering impact of secondary aggressors

Back-End Design

Hosted in Virtual Platform

Tutorial

Adding machine learning to the mix of EDA optimization algorithms

Presented In-Person

Research Manuscript

AdEle: An Adaptive Congestion-and-Energy-Aware Elevator Selection for Partially Connected 3D NoCs

EDA

In-Package and On-Chip Communication and Networks-on-Chip

Presented In-Person

Research Manuscript

ADROIT: An Adaptive Dynamic Refresh Optimization Framework for DRAM Energy Saving in DNN Training

Design

AI/ML System Design

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Presentations

Aging aware Static Timing Analysis

Back-End Design

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Presentations

Aging Timing Analysis Based on EMPYREAN-XTime

Back-End Design

Presented In-Person

Keynote

AI, Machine Learning, Deep Learning: Where are the Real Opportunities for the EDA Industry?

Hosted in Virtual Platform

Presented In-Person

Research Manuscript

AID: Attesting the Integrity of Deep Neural Networks

Design

AI/ML System Design

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Presentations

Algorithm to RTL: A Faster Path to Implementation

Presented In-Person

Special Session (Research Track)

Always-On modules demonstrate that tinyML is already here!

Embedded Systems

Machine Learning/AI

Hosted in Virtual Platform

Networking Reception

Work-in-Progress Poster

Ambrosia: Reduction in Data Transfer from Sensor to Server for Increased Lifetime of IoT Sensor Nodes

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

AMS Verification of HBMPHY: Challenges & Solutions - 12nm Process Node

Presented In-Person

Research Manuscript

An Automated and Process-Portable Generator for Phase-Locked Loop

Design

Digital and Analog Circuits

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Poster Networking Reception

An Automated Approach to Pre-empt Clock-Divergence & Achieve Predictable Timing Closure

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

An automated decision-making tool to accelerate Computational SRAM design for memory-bound applications

Presented In-Person

Research Manuscript

An Efficient Algorithm for Sparse Quantum State Preparation

Design

Quantum Computing

Hosted in Virtual Platform

Networking Reception

Work-in-Progress Poster

An Efficient Cell Capacitor Compact Modeling and Application for High-speed DRAM Design

Presented In-Person

Research Manuscript

An Energy-Efficient Low-Latency 3D-CNN Accelerator Leveraging Temporal Locality, Full Zero-Skipping, and Hierarchical Load Balance

Design

AI/ML System Design

Hosted in Virtual Platform

Networking Reception

Work-in-Progress Poster

An In-Memory Analog Computing Co-Processor for Energy-Efficient CNN Inference on Mobile Devices

Presented In-Person

Research Manuscript

An Intelligent Video Processing Architecture for Edge-cloud Video Streaming

Design

Design of Cyber-physical Systems and IoT

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Presentations

Analog Fault Simulation for Automotive Sensor Designs

Front-End Design

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Poster Networking Reception

Analog in memory computing optimization with TOPS/W Methodology

Presented In-Person

Research Manuscript

Analyzing and Improving Fault Tolerance of Learning-Based Navigation Systems

Autonomous Systems

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

Andes ACE feature extended on Menta eFPGA for RISC-V cores ISA reconfigurability in the field

Presented In-Person

Research Manuscript

Anonymous: Constructing Rectilinear Minimum Steiner Tree via Reinforcement Learning

EDA

Physical Design and Verification, Lithography and DFM

Hosted in Virtual Platform

Research Manuscript

AppealNet: An Efﬁcient and Highly-Accurate Edge/Cloud Collaborative Architecture for DNN Inference

Design

Design of Cyber-physical Systems and IoT

Hosted in Virtual Platform

Research Manuscript

Application of Deep Reinforcement Learning to Dynamic Verification of DRAM Designs

EDA

Design Verification and Validation

Hosted in Virtual Platform

Research Manuscript

Approximate Equivalence Checking of Noisy Quantum Circuits

EDA

Design Verification and Validation

Hosted in Virtual Platform

Tutorial

Approximate Synthesis: State-of-the-art and Future Directions

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Architectural Formal Sign-Off of Compression System Data Coherency

Front-End Design

Hosted in Virtual Platform

Research Manuscript

Architecture-aware Precision Tuning with Multiple Number Representation Systems*

Embedded Systems

Embedded Software

Hosted in Virtual Platform

Research Manuscript

ASBP: Automatic Structured Bit-Pruning for RRAM-based NN Accelerator

Design

AI/ML System Design

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Poster Networking Reception

Attaining Consistent RTL Quality and Improving Development Cycles with GIT Continuous Integration Tools

Presented In-Person

Research Manuscript

Attentional Transfer is All You Need: Technology-aware Layout Pattern Generation

EDA

Physical Design and Verification, Lithography and DFM

Hosted in Virtual Platform

Research Manuscript

Automated Compensation Scheme Design for Operational Amplifier via Bayesian Optimization

Design

Digital and Analog Circuits

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Poster Networking Reception

Automated Generation of Current Controlled Oscillator (CCO) Layout using Template Reuse Flow

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Automatic Clock Gating and Closed-Loop DVFS for 4nm Exynos Mobile SoC Processor

Front-End Design

Hosted in Virtual Platform

Panel

Autonomous Robot Design: How can EDA help?

EDA

Hosted in Virtual Platform

Presented In-Person

Research Manuscript

AutoSVA: Democratizing Formal Verification of RTL Module Interactions

EDA

Design Verification and Validation

Presented In-Person

Special Session (Research Track)

Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications

EDA

Machine Learning/AI

Hosted in Virtual Platform

Research Manuscript

BayesFT: Bayesian Optimization for Fault Tolerant Neural Network Architecture

Design

Approximate Computing for AI/ML

Hosted in Virtual Platform

Research Manuscript

Bayesian Inference Based Robust Computing on Memristor Crossbar

Design

Emerging Device Technologies

Hosted in Virtual Platform

Research Manuscript

BHDL: A Lucid, Expressive, and Embedded Programming Language and System for PCB Designs

EDA

System-on-Chip Design Methodology

Presented In-Person

Research Manuscript

Bit-Slicing the Hilbert Space: Scaling Up Accurate Quantum Circuit Simulation

Design

Quantum Computing

Hosted in Virtual Platform

Research Manuscript

Bitwidth-Optimized Energy-Efficient FFT Design via Scaling Information Propagation

Embedded Systems

Embedded System Design Methodologies

Hosted in Virtual Platform

Research Manuscript

BlockGNN: Towards Efficient GNN Acceleration Using Block-Circulant Weight Matrices

Design

AI/ML System Design

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Presentations

BLOF:A Binary Group List based Low Overhead Index Structure and Fast File Management Method

Embedded Systems

Hosted in Virtual Platform

Research Manuscript

BLOwing Trees to the Ground: Layout Optimization of Decision Trees on Racetrack Memory

Embedded Systems

Embedded Memory, Storage and Networking

Hosted in Virtual Platform

Research Manuscript

BRAHMS: Beyond Conventional RRAM-based Neural Network Accelerators Using Hybrid Analog Memory System

Design

AI/ML System Design

Hosted in Virtual Platform

Special Session (Research Track)

Building scalable variational circuit training for machine learning tasks

Design

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Poster Networking Reception

CANCELLED End-to-End Solution for structured implementation of high-speed data buses

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

CANCELLED: A Single Solution for Scanning, Tracking Inventory, Transactions, and Recharging

Presented In-Person

Networking Reception

Work-in-Progress Poster

CANCELLED: ARGOS: an Adaptive and ReGion-scale knowledge distillation for Object recognition Systems

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

CANCELLED: Beyond Lint

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

CANCELLED: Fast Tracking a Federal Authentication Solution for Secure Facilities

Presented In-Person

Networking Reception

Work-in-Progress Poster

CANCELLED: IO Performance Modeling for Communication Workloads

Presented In-Person

Research Manuscript

CANCELLED: Leveraging Noise and Aggressive Quantization of In-Memory Computing for Robustness Improvement of DNN Hardware Against Adversarial Input and Weight Attacks

Security

Hardware Security: Attack and Defense

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

CANCELLED: Modernizing a Nationwide Indoor/Outdoor Package Sorting System

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

CANCELLED: Modernizing Public Infrastructure with Interactive Devices

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

CANCELLED: Resolution of Verification bottleneck by Functional Coverage Automation

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

CANCELLED: Rethinking New Product Introduction to Better Align to Client Needs

Presented In-Person

Networking Reception

Work-in-Progress Poster

CANCELLED: RoHNAS–When Robustness Meets HW-Aware NAS: A Neural Architecture Search Framework with Conjoint Optimization for Adversarial Robustness and Hardware Efficiency of Convolutional and Capsule Networks

Presented In-Person

Networking Reception

Work-in-Progress Poster

CANCELLED: RVfplib: A Fast and Compact Open-Source Floating-Point Emulation Library for Tiny RISC-V Processors

Presented In-Person

Networking Reception

Work-in-Progress Poster

CANCELLED: SonicFFT: A system architecture for ultrasonic-based FFT acceleration

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

CANCELLED: Stress Testing to Survive an Industrial Gas Turbine

Presented In-Person

Research Manuscript

CascadeHD: Efficient Many-Class Learning Framework Using Hyperdimensional Computing

Design

AI/ML System Design

Hosted in Virtual Platform

Research Manuscript

CDAR-DRAM: An In-situ Charge Detection and Adaptive Data Restoration DRAM Architecture for Performance and Energy Efficiency Improvement

Embedded Systems

Embedded Memory, Storage and Networking

Hosted in Virtual Platform

TechTalk

Charting the Path to 3nm & More than Moore

Hosted in Virtual Platform

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Christmas Lights Displays As Embedded Systems

Embedded Systems

Presented In-Person

Special Session (Research Track)

CIRCT - Circuit IR Compilers and Tools

EDA

Machine Learning/AI

Hosted in Virtual Platform

Research Manuscript

Circuit Connectivity Inspired Neural Network for Analog Mixed-Signal Functional Modeling

Design

Digital and Analog Circuits

Hosted in Virtual Platform

Research Manuscript

CLAppED: A Design Framework for Implementing Cross-Layer Approximation in FPGA-based Embedded Systems

Design

Approximate Computing for AI/ML

Hosted in Virtual Platform

Research Manuscript

Classifying Computations on Multi-Tenant FPGAs

Security

Hardware Security: Primitives, Architecture, Design & Test

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Presentations

Clocking Methods with Focus on PCIe Gen4

Back-End Design

Presented In-Person

Tutorial

Closing the Hardware Software CoDesign Loop with Open Source Flows

EDA

Presented In-Person

SKY Talk

Cloud & AI technologies for faster, secure semiconductor supply chains

Hosted in Virtual Platform

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

Cloud Infrastructure for Remote and Scalable EDA Hardware Training

Presented In-Person

Research Manuscript

Cocktail: Learn a Better Neural Network Controller from Multiple Experts via Adaptive Mixing and Robust Distillation

Design

Design of Cyber-physical Systems and IoT

Presented In-Person

Networking Reception

Work-in-Progress Poster

CoDR: Computation and Data Reuse Aware CNN Accelerator

Presented In-Person

Research Manuscript

Cognitive Correlative Encoding for Genome Sequence Matching in Hyperdimensional System

Design

Approximate Computing for AI/ML

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Presentations

Comprehensive processor security verification: A CIA problem

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Poster Networking Reception

Constraints based CDC Sign-Off methodology

Presented In-Person

Networking Reception

Work-in-Progress Poster

Context-Aware Task Handling in Resource-Constrained Robots with Virtualization

Presented In-Person

Research Manuscript

Control Variate Approximation for DNN Accelerators

Design

Approximate Computing for AI/ML

Presented In-Person

Special Session (Research Track)

Convergence of SoC architecture and semiconductor manufacturing through AI/ML systems

Design

Machine Learning/AI

Hosted in Virtual Platform

Research Manuscript

COSAIM: Counter-based Stochastic-behaving Approximate Integer Multiplier for Deep Neural Networks

Design

Approximate Computing for AI/ML

Presented In-Person

Research Manuscript

CoSPARSE: A Software and Hardware Reconfigurable SpMV Framework for Graph Analytics

Design

SoC, Heterogeneous, and Reconfigurable Architectures

Presented In-Person

Research Manuscript

Cross-Device Profiled Side-Channel Attacks using Meta-Transfer Learning

Security

Hardware Security: Attack and Defense

Hosted in Virtual Platform

SKY Talk

Cross-Disciplinary Innovations Required for the Future of Computing

Hosted in Virtual Platform

Presented In-Person

Tutorial

Crossbar memory systems for machine learning: circuits, architecture, and evaluation frameworks

Presented In-Person

Research Manuscript

CrossLight: A Cross-Layer Optimized Silicon Photonic Neural Network Accelerator

Design

AI/ML System Design

Presented In-Person

Research Manuscript

CuckoOnsai: An Efficient Memory Authentication Using Amalgam of Cuckoo Filters and Integrity Trees

Security

Hardware Security: Primitives, Architecture, Design & Test

Presented In-Person

Research Manuscript

DANCE: Differentiable Accelerator/Network Co-Exploration

EDA

System-on-Chip Design Methodology

Presented In-Person

Research Manuscript

Dancing along Battery: Enabling Transformer with Run-time Reconfigurability on Mobile Devices

Design

AI/ML System Design

Hosted in Virtual Platform

Research Manuscript

Dataflow Mirroring: Architectural Support for Highly Efficient Fine-Grained Spatial Multitasking on Systolic-Array NPUs

Design

AI/ML System Design

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Deep data for faster silicon bring-up, characterization, and qualification with higher confidence

Presented In-Person

Research Manuscript

Deep Integration of Circuit Simulator and SAT Solver

EDA

RTL/Logic Level and High-level Synthesis

Hosted in Virtual Platform

Research Manuscript

DeepStrike: Remotely-Guided Fault Injection Attacks on DNN Accelerator in Cloud-FPGA

Security

Embedded and Cross-Layer Security

Hosted in Virtual Platform

TechTalk

Delivering Systemic Innovation to Power the Era of SysMoore

Hosted in Virtual Platform

Presented In-Person

Networking Reception

Work-in-Progress Poster

DeltaNet: High-Performance Federated Learning with Hybrid Data & Model Parallelism

Presented In-Person

Tutorial

Design and Consumption of IPs for Fail-Safe Automotive ICs

Presented In-Person

DAC Pavilion Panels

Design and Verification Engineer 2.0—A New Generation or a Pipe Dream?

Presented In-Person

Networking Reception

Work-in-Progress Poster

Design Context Aware Electromigration Analysis Methodology to Overcome BEOL Interconnect Scaling Induced Reliability Risk for Advanced Process Technology

Presented In-Person

Research Manuscript

Designing a 2048-Chiplet, 14336-Core Waferscale Processor

Design

SoC, Heterogeneous, and Reconfigurable Architectures

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Designing IP To Achieve Optimal Low Power Using Protocol Defined Low Power States

Front-End Design

Hosted in Virtual Platform

Networking Reception

Work-in-Progress Poster

Detecting security and privacy threats in home IoT networks through traffic profiling

Presented In-Person

Networking Reception

Work-in-Progress Poster

Determining the Multiplicative Complexity of Boolean Functions using SAT

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Diagnostic Coverage of Memory IP with Fault Injection Simulation using TestMAX CustomFault Simulator

Hosted in Virtual Platform

Research Manuscript

DIALED: Data Integrity Attestation for Low-end Embedded Devices

Security

Embedded and Cross-Layer Security

Presented In-Person

Analyst Review

Digitalization—The Return to Outsize Growth for the Semiconductor Industry

Hosted in Virtual Platform

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

DIMM Level Verification Methodology for DRAM Custom DFT

Front-End Design

Hosted in Virtual Platform

Research Manuscript

DirectFuzz: Automated Test Generation for RTL Designs using Directed Graybox Fuzzing

EDA

Design Verification and Validation

Hosted in Virtual Platform

Research Manuscript

Distilling Arbitration Logic from Traces using Machine Learning: A Case Study on NoC*

EDA

In-Package and On-Chip Communication and Networks-on-Chip

Hosted in Virtual Platform

Research Manuscript

Distributed Memory Guard: Enabling Secure Enclave Computing in NoC-based Architectures

Security

Embedded and Cross-Layer Security

Presented In-Person

Research Manuscript

DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networks*

EDA

Analog Design, Simulation, Verification and Test

Presented In-Person

Special Session (Research Track)

Drug Discovery Approaches using Quantum Machine Learning

Design

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Poster Networking Reception

Dual Feature Vector Hetero Graph Neural Network (DFV-GNN) based Post-Layout Parasitic Estimation

Presented In-Person

Research Manuscript

DyGNN: Algorithm and Architecture Support of Dynamic Pruning for Graph Neural Networks

Design

SoC, Heterogeneous, and Reconfigurable Architectures

Hosted in Virtual Platform

Research Manuscript

Dynamic Chip Clustering and Task Allocation for Real-time Flash

Embedded Systems

Time-Critical System Design

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

Early Layout Area and PLS Estimation by Designers

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

ECO patch generation & stitching to facilitate concurrent ECOs in High Performance Processor Designs

Back-End Design

Presented In-Person

Research Manuscript

Eco-feller: Minimizing the Energy Consumption of Random Forest Algorithm by an Eco-pruning Strategy over MLC NVRAM

Embedded Systems

Embedded Software

Hosted in Virtual Platform

Additional Meeting

EDA Growth Accelerates as Moore’s Law Slows

Networking Reception

Work-in-Progress Poster

EdgenAI: Distributed Inference with Local Edge Devices and Minimum Latency

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Efficient Data Exchange Towards Faster Functional Safety Development

Front-End Design

Hosted in Virtual Platform

Research Manuscript

Efficient Error-Correcting-Code Mechanism for High-Throughput Memristive Processing-in-Memory

Embedded Systems

Near-Memory and In-Memory Computing

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

Efficient High-Sigma Verification of Standard Cell Libraries

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

Efficient Impedance Discontinuity Optimization Technique for High Speed Interfaces

Presented In-Person

Research Manuscript

Efficient Implementation of Finite Field Arithmetic for Binary Ring-LWE Post-Quantum Cryptography Through a Novel Lookup-Table-Like Method

Security

Hardware Security: Primitives, Architecture, Design & Test

Presented In-Person

Networking Reception

Work-in-Progress Poster

Efficient Real-Time Object Detection with Adaptive Image Scaling and Cropping

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Efficient System PDN Analysis Methodat Pre-Layout Stage

Back-End Design

Hosted in Virtual Platform

Research Manuscript

Efficient Tunstall Decoders for Compressed Deep Neural Network

Design

AI/ML System Design

Hosted in Virtual Platform

Research Manuscript

EImprove - Optimizing Energy and Comfort in Buildings based on Formal Semantics and Reinforcement Learning

Embedded Systems

Embedded System Design Methodologies

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Poster Networking Reception

Embedded Security optimized with eFPGA

Presented In-Person

Research Manuscript

EMGraph: Fast Learning-Based Electromigration Analysis for Multi-Segment Interconnect Using Graph Convolution Networks

EDA

Manufacturing Test and Reliability

Presented In-Person

Tutorial

Enabling FV and Simulation using Functional Specifications: The Open-Source ILA Methodology

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Enabling Hierarchical Flattened Functional ECO Flow for Quality Patch Generation with Runtime Benefits

Back-End Design

Hosted in Virtual Platform

Research Manuscript

Enabling On-Device Model Personalization for Ventricular Arrhythmias Detection by Generative Adversarial Networks

Embedded Systems

Embedded System Design Methodologies

Hosted in Virtual Platform

Research Manuscript

Enabling On-Device Self-supervised Contrastive Learning With Selective Data Contrast

Embedded Systems

Embedded Software

Hosted in Virtual Platform

Research Manuscript

Enabling the Design of Behavioral Systems-on-Chip

EDA

System-on-Chip Design Methodology

Hosted in Virtual Platform

Special Session (Research Track)

End-to-End Secure SoC Lifecycle Management

Security

Hosted in Virtual Platform

Presented In-Person

Networking Reception

Work-in-Progress Poster

Energy Harvesting Aware Multi-hop Routing and Energy Allocation in Distributed IoT System based on Multi-agent Reinforcement Learning

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Enhanced Analytics and Reporting for Triage and Sign-off Timing

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Enhanced Hyperscaling of Data Centers using In-Chip Monitoring & Sensing Fabrics

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

Ensuring Completeness of Formal Verification with GapFree: Are we done yet?

Hosted in Virtual Platform

Presented In-Person

Panel

Environmentally Sustainable Computing

Design

Hosted in Virtual Platform

Presented In-Person

Research Manuscript

Evolved Neural-Hardware-Compiler Co-Design

Design

AI/ML System Design

Presented In-Person

Research Manuscript

Exact Neural Networks from Inexact Multipliers via Fibonacci Weight Encoding

Design

Approximate Computing for AI/ML

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Exchanging EDA data for AI/ML using Standard API

Machine Learning/AI

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Expediting Data Converter Layouts using Design Planning & Analysis (DPA) Automation

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

Extended Power Connectivity Solution for CPF based Low Power Simulation

Presented In-Person

Research Manuscript

F-CAD: A Framework to Explore Hardware Accelerators for Codec Avatar Decoding

Design

AI/ML System Design

Presented In-Person

Research Manuscript

F3D: Accelerating 3D Convolutional Neural Networks in Frequency Space Using ReRAM

Design

AI/ML System Design

Hosted in Virtual Platform

Research Manuscript

Falcon Down: Breaking the Falcon Post-Quantum Signature Scheme through Side-Channel Attacks

Security

Hardware Security: Attack and Defense

Presented In-Person

Networking Reception

Work-in-Progress Poster

FASCINET: Fully Automated Single-Board Computer Generator Using a Neural Network Based Datasheet Scrubber

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

Fast and Accurate DvD aware Timing Analysis

Presented In-Person

Research Manuscript

Fault-free: A Fault-resilient Deep Neural Network Accelerator based on Realistic ReRAM Devices

Design

AI/ML System Design

Hosted in Virtual Platform

Research Manuscript

FedLight: Federated Reinforcement Learning for Autonomous Multi-Intersection Traffic Signal Control

Autonomous Systems

Hosted in Virtual Platform

Networking Reception

Work-in-Progress Poster

Finding Optimal Implementations of Non-native CNOT Gates using SAT

Presented In-Person

Research Manuscript

FIXAR: A Fixed-Point Deep Reinforcement Learning Platform with Quantization-Aware Training and Adaptive Parallelism

Design

AI/ML System Design

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

Formal Verification of Safety Mechanisms | Infineon Technologies

Presented In-Person

Research Manuscript

Formulating Data-arrival Synchronizers in Integer Linear Programming for CGRA Mapping

Design

SoC, Heterogeneous, and Reconfigurable Architectures

Hosted in Virtual Platform

Research Manuscript

Fortifying RTL Locking Against Oracle-Less (Untrusted Foundry) and Oracle-Guided Attacks

Security

Hardware Security: Attack and Defense

Presented In-Person

Tutorial

From EDA to TEEs, Security Tools for Understanding and Mitigating Side-Channel and Fault Injection Attacks

Presented In-Person

Special Session (Research Track)

Functional Criticality Classification of Structural Faults in AI Accelerators

Design

Machine Learning/AI

Hosted in Virtual Platform

Networking Reception

Work-in-Progress Poster

Games, Dollars, Splits: A Game-Theoretic Analysis of Split Manufacturing

Presented In-Person

Research Manuscript

GCiM: A Near-Data Processing Accelerator for Graph Construction

Embedded Systems

Near-Memory and In-Memory Computing

Hosted in Virtual Platform

Research Manuscript

Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration*

Design

AI/ML System Design

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Get more out of your UVM register Layer!

Front-End Design

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Presentations

Getting started on Cloud Playbook

Cloud

Presented In-Person

Special Session (Research Track)

Getting the Most out of your Circuits with Heterogeneous Logic Synthesis

EDA

Machine Learning/AI

Hosted in Virtual Platform

Research Manuscript

gGuard: Enabling Leakage-Resilient Memory Isolation in GPU-accelerated Autonomous Embedded Systems

Autonomous Systems

Presented In-Person

Networking Reception

Work-in-Progress Poster

Glitch and Level Detection Algorithms for Analog Mixed-Signal Verification Coverage Management

Presented In-Person

Research Manuscript

GNN4IP: Graph Neural Network for Hardware Intellectual Property Piracy Detection

Security

Hardware Security: Primitives, Architecture, Design & Test

Hosted in Virtual Platform

Research Manuscript

GNNerator: A Hardware/Software Framework for Accelerating Graph Neural Networks

Design

SoC, Heterogeneous, and Reconfigurable Architectures

Presented In-Person

Research Manuscript

GPU-accelerated Path-based Timing Analysis

EDA

Digital Design, Timing and Simulation

Hosted in Virtual Platform

Keynote

GPUs, Machine Learning, and EDA

Hosted in Virtual Platform

Presented In-Person

Research Manuscript

GraphSpy: Fused Program Semantic Embedding through Graph Neural Networks for Memory Efficiency

Design

AI/ML System Design

Hosted in Virtual Platform

Networking Reception

Work-in-Progress Poster

GridNetOpt: Fast Full-Chip EM-Aware IR Drop Constrained Power Grid Optimization via Deep Neural Networks

Presented In-Person

Networking Reception

Work-in-Progress Poster

Guiding Global Placement with Reinforcement Learning

Presented In-Person

Additional Meeting

HACK@DAC Final Competition

Research Manuscript

HADFL: Heterogeneity-aware Decentralized Federated Learning Framework

Design

AI/ML System Design

Hosted in Virtual Platform

Networking Reception

Work-in-Progress Poster

HammerFilter: Robust Protection and Low Hardware Overhead Method for Row-Hammering

Presented In-Person

DAC Pavilion Panels

Handling SoC Verification: Changing the Paradigm in Verification Approaches

Presented In-Person

Special Session (Research Track)

Hardware-aware Real-time Myocardial Segmentation Quality Control in Contrast Echocardiography

Design

Machine Learning/AI

Hosted in Virtual Platform

Special Session (Research Track)

Hardware/Software Design Methods Co-Synthesis and Optimization for Autonomous Systems

Autonomous Systems

Design

Hosted in Virtual Platform

Research Manuscript

HDTest: Differential Fuzz Testing of Brain-Inspired Hyperdimensional Computing

Design

Emerging Models of Computation

Hosted in Virtual Platform

Research Manuscript

Helios: Heterogeneity-Aware Federated Learning with Dynamically Balanced Collaboration

Design

AI/ML System Design

Hosted in Virtual Platform

Research Manuscript

Heterogeneous Monolithic 3D ICs: EDA Solutions, and Power, Performance, Cost Tradeoffs

Design

SoC, Heterogeneous, and Reconfigurable Architectures

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

High Bandwidth All-Digital Clock and Data Recovery Architecture

Hosted in Virtual Platform

Research Manuscript

High-Performance FPGA-based Accelerator for Bayesian Neural Networks

Design

AI/ML System Design

Presented In-Person

Research Manuscript

HLock: Locking IPs at the High-Level Language

Security

Hardware Security: Attack and Defense

Presented In-Person

Panel

Homomorphic Computing as a Foundational Technology: Theory, Practice, and Future Business

Security

Hosted in Virtual Platform

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

How AI and Cloud enable a virtuous cycle in silicon design and manufacturing

Cloud

Machine Learning/AI

Presented In-Person

DAC Pavilion Panels

How System Companies are Re-shaping requirements for EDA

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Hybrid Emulation Methodology for SSD Design

Presented In-Person

Research Manuscript

I/O-GUARD: Hardware/Software Co-Design for I/O Virtualization with Guaranteed Real-time Performance

Embedded Systems

Time-Critical System Design

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Presentations

Identifying Security Weaknesses in Electronic Designs using a Standardized Methodology

Security

Presented In-Person

Additional Meeting

IEEE CEDA Distinguished Speaker Luncheon featuring Dr. Tsu-Jae King Liu "Semiconductor Device Innovation for the Age of Ambient Intelligence"

Research Manuscript

In-Hardware Learning of Multilayer Spiking Neural Networks on a Neuromorphic Processor

Design

Emerging Models of Computation

Hosted in Virtual Platform

Special Session (Research Track)

Independent Verification and Validation of Security-Aware EDA Tools and IP

Security

Hosted in Virtual Platform

Presented In-Person

Additional Meeting

Industry Liaison Committee Breakfast

Designer, IP and Embedded Systems Track Presentations

Innovative Techniques to Accelerate Error Handling Verification of Complex Systems

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Input Qualification Methodology Helps Achieve System Level Power Numbers 8x Faster

Hosted in Virtual Platform

Research Manuscript

InstantNet: Automated Generation and Deployment of Instantaneously Switchable-Precision Networks

Design

AI/ML System Design

Presented In-Person

Special Session (Research Track)

Integration of IC Design Changes into a BlockChain for Traceability in AISS Design Flow

Security

Hosted in Virtual Platform

Research Manuscript

Interactive Analog Layout Editing with Instant Placement Legalization

EDA

Analog Design, Simulation, Verification and Test

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

IP Enabling the Intended Function. The Unloved IP.

Presented In-Person

Research Manuscript

ISA Modeling with Trace Notation for Context Free Property Generation

EDA

Design Verification and Validation

Presented In-Person

Research Manuscript

JPDHeap: A JVM Heap Design for PM-DRAM Memories

Embedded Systems

Near-Memory and In-Memory Computing

Hosted in Virtual Platform

Special Session (Research Track)

kCC-Net for Compression of Biomedical Image Segmentation Networks

Design

Machine Learning/AI

Hosted in Virtual Platform

Research Manuscript

KV-SSD: What is it Good For?

Embedded Systems

Embedded Memory, Storage and Networking

Presented In-Person

Late Breaking Results Poster

Networking Reception

Late Breaking Results: An Effective Legalization Algorithm for Heterogeneous FPGAs with Complex Constraints

Presented In-Person

Late Breaking Results Poster

Networking Reception

Late Breaking Results: Attention in Graph2Seq Neural Networks towards Push-Button Analog IC Placement

Presented In-Person

Late Breaking Results Poster

Networking Reception

Late Breaking Results: Heterogeneous Circuit Layout Centerline Extraction for Mask Verification

Presented In-Person

Late Breaking Results Poster

Networking Reception

Late Breaking Results: Incremental 3D Global Routing Considering Cell Movement

Presented In-Person

Late Breaking Results Poster

Networking Reception

Late Breaking Results: Novel Discrete Dynamic Filled Function Algorithm for Acyclic Graph Partitioning

Presented In-Person

Late Breaking Results Poster

Networking Reception

Late Breaking Results: Parallelizing Net Routing with cGANs

Presented In-Person

Research Manuscript

Learning Pareto-Frontier Resource Management Policies for Heterogeneous SoCs: A Information-Theoretic Approach

Embedded Systems

Embedded System Design Methodologies

Hosted in Virtual Platform

Networking Reception

Work-in-Progress Poster

Learning Quantum Circuit Errors Based on Error Propagation

Presented In-Person

Research Manuscript

LENS: Layer Distribution Enabled Neural Architecture Search in Edge-Cloud Hierarchies

Design

Design of Cyber-physical Systems and IoT

Hosted in Virtual Platform

Research Manuscript

Load-Step: A Precise TrustZone Execution Control Framework for Exploring New Side-channel Attacks Like Flush+Evict

Security

Embedded and Cross-Layer Security

Hosted in Virtual Platform

Research Manuscript

Local Bayesian Optimization for Analog Circuit Sizing

EDA

Analog Design, Simulation, Verification and Test

Hosted in Virtual Platform

Research Manuscript

LolliRAM: A Cross-Layer Design to Exploit Data Locality in Oblivious RAM

Embedded Systems

Embedded Memory, Storage and Networking

Hosted in Virtual Platform

Research Manuscript

Low-Cost and Effective Fault-Tolerance Enhancement Techniques for Emerging Memories-Based Deep Neural Networks

Design

AI/ML System Design

Presented In-Person

Research Manuscript

Low-Cost Lithography Hotspot Detection with Active Entropy Sampling and Model Calibration

EDA

Manufacturing Test and Reliability

Presented In-Person

Research Manuscript

LUT-Based Optimization For ASIC Design Flow

EDA

RTL/Logic Level and High-level Synthesis

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

Machine learning Assisted Design Rule Debug and Rule Ranking Automation

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Machine Learning Based Efficient Regression Test Framework in SOC Verification

Front-End Design

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Presentations

Machine Learning based IR Drop Prediction on ECO Revised Designs for Faster Convergence

Back-End Design

Hosted in Virtual Platform

Special Session (Research Track)

Mask Synthesis in the Era of GPU Computing and Deep Learning

EDA

Machine Learning/AI

Hosted in Virtual Platform

Presented In-Person

Special Session (Research Track)

Mastering the three pillars of accelerator design for Deep Learning

Design

Machine Learning/AI

Hosted in Virtual Platform

Research Manuscript

MAT: Processing In-Memory Acceleration for Long-Sequence Attention

Embedded Systems

Near-Memory and In-Memory Computing

Presented In-Person

Research Manuscript

Max-PIM: Fast and Efficient Max/Min Searching in DRAM

Embedded Systems

Near-Memory and In-Memory Computing

Hosted in Virtual Platform

Research Manuscript

MEGATRON: Software-Managed Device TLB for Shared-Memory FPGA Virtualization

Design

SoC, Heterogeneous, and Reconfigurable Architectures

Hosted in Virtual Platform

Research Manuscript

MeLoPPR: Software/Hardware Co-design for Memory-efficient Low-latency Personalized PageRank

Embedded Systems

Embedded System Design Methodologies

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Poster Networking Reception

Memory Peripheral Standard Cell Architecture Optimization using DTCO under Strong Area Restriction

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Methodology for Accurate Analysis of Dynamic Voltage Drop Induced Clock Jitter for Improved PPA

Back-End Design

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Presentations

Methodology for early timing and floorplanning closure in custom circuit design

Back-End Design

Presented In-Person

Research Manuscript

Micro-bumping, Hybrid Bonding, or Monolithic? A PPA Study for Heterogeneous 3D IC Options

Design

SoC, Heterogeneous, and Reconfigurable Architectures

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Middle of Layer Routing Enablement for Increasing Routing Resource

Back-End Design

Hosted in Virtual Platform

Research Manuscript

Mitigating Crosstalk in Quantum Computers through Commutativity-Based Instruction Reordering

Design

Quantum Computing

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Presentations

Mitigating Variability Challenges of IPs for Robust Design

Presented In-Person

Research Manuscript

MobileSwap: Cross-Device Memory Swapping for Mobile Devices

Embedded Systems

Embedded Memory, Storage and Networking

Hosted in Virtual Platform

Networking Reception

Monday Networking Reception Honoring Women in Electronic Design

Designer, IP and Embedded Systems Track Presentations

Monica - On-chip Monitoring Systems Characterization

Embedded Systems

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Poster Networking Reception

MOVE TO VIRTUAL: LabReplay: Efficient Replay of Post-Silicon Debug for High Performance Microprocessor Designs

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

MOVE TO VIRTUAL: NEXA: Cloud Native Platform for Collaborative Hardware Logic Design in Step-wise Refinement Implementation Flows

Presented In-Person

Research Manuscript

Move-On-Modify: An Efficient yet Crash-Consistent Update Strategy for Interlaced Magnetic Recording

Embedded Systems

Embedded Memory, Storage and Networking

Hosted in Virtual Platform

Workshop

MOVED TO VIRTUAL: 2nd ROAD4NN Workshop: Research Open Automatic Design for Neural Networks

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

MOVED TO VIRTUAL: Innovative In-Situ Slack Monitor (IS2M) Design for Dynamic Detection of Voltage Temperature Ageing Change.

Presented In-Person

Research Manuscript

MOVED TO VIRTUAL: Scaling up HBM Efficiency of Top-K SpMV for Approximate Embedding Similarity on FPGAs

Design

Approximate Computing for AI/ML

Hosted in Virtual Platform

Special Session (Research Track)

MOVED TO VIRTUAL: Security Beyond CMOS: Opportunities and Challenges of Emerging Devices

Design

Security

Hosted in Virtual Platform

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

MOVED TO VIRTUAL: The Reality and Opportunities of Semiconductor Design on the Cloud

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

Multi-core System Verification Using Uvm Portable Stimulus

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

Multi-Physics Simulation Techniques toward Electromagnetic Side-Channel Attack Assessments on IC Chip Assembly

Presented In-Person

Research Manuscript

MyML: User-Driven Machine Learning

Embedded Systems

Embedded System Design Methodologies

Presented In-Person

Research Manuscript

Network-on-Interposer Design for Agile Neural-Network Processor Chip Customization

EDA

In-Package and On-Chip Communication and Networks-on-Chip

Hosted in Virtual Platform

Research Manuscript

Neural Pruning Search for Real-Time Object Detection of Autonomous Vehicles

Autonomous Systems

Presented In-Person

Research Manuscript

NeurFill: Migrating Full-Chip CMP Simulators to Neural Networks for Model-Based Dummy Filling Synthesis

EDA

Physical Design and Verification, Lithography and DFM

Hosted in Virtual Platform

Research Manuscript

Neuromorphic Algorithm-hardware Codesign for Temporal Pattern Learning

Design

Emerging Models of Computation

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Poster Networking Reception

New file system to automatically "spill" workloads across Datacenter and Cloud

Presented In-Person

Research Manuscript

New Predictor-Based Attacks in Processors

Security

Hardware Security: Attack and Defense

Hosted in Virtual Platform

Research Manuscript

New Regular Expressions on Old Accelerators

EDA

System-on-Chip Design Methodology

Presented In-Person

Research Manuscript

Noise-Robust Deep Spiking Neural Networks with Temporal Information

Design

Emerging Models of Computation

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Poster Networking Reception

Novel Chip-Package-System Power Noise Analysis with RTL Power Profiling

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Novel end to end Non-coherent access mechanism on X86 SOC

Front-End Design

Hosted in Virtual Platform

Networking Reception

Work-in-Progress Poster

Novel Static Timing Analysis considering Dynamic Voltage Drop

Presented In-Person

Special Session (Research Track)

NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning

EDA

Hosted in Virtual Platform

Research Manuscript

Obfuscated Priority Assignment to CAN-FD Messages with Dependencies: A Swapping-based and Affix-Matching Approach

Design

Design of Cyber-physical Systems and IoT

Hosted in Virtual Platform

Research Manuscript

On The Efficiency of Sparse-Tiled Tensor Graph Processing For Low Memory Usage

Embedded Systems

Embedded Software

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Poster Networking Reception

On the Energy Efficiency of Machine Learning Frameworks

Presented In-Person

Networking Reception

Work-in-Progress Poster

On the Impact of Electrical Masking and Timing Analysis on Soft Error Rate Estimation in Deep Submicron Technologies

Presented In-Person

Research Manuscript

On the Intrinsic Robustness of NVM Crossbars against Adversarial Attacks

Security

Hardware Security: Attack and Defense

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

On-Chip Dynamic IR Drop Induced Deterministic Jitter Analysis

Back-End Design

Hosted in Virtual Platform

Research Manuscript

On-device Malware Detection using Performance-Aware and Robust Collaborative Learning

Security

Embedded and Cross-Layer Security

Hosted in Virtual Platform

Research Manuscript

OpenMem: Hardware/Software Cooperative Management for Mobile Memory System

Embedded Systems

Embedded Memory, Storage and Networking

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Optical and Thermal Simulations for Integrated III-V/Si Heterogeneous Lasers on Silicon Photonics System

Back-End Design

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Presentations

Optimal Function Clock Aware Scan Methodology

Back-End Design

Hosted in Virtual Platform

Research Manuscript

Optimal Memory Allocation and Scheduling for DMA Data Transfers under the LET Paradigm

Embedded Systems

Time-Critical System Design

Hosted in Virtual Platform

Research Manuscript

Optimized Polynomial Multiplier Architectures forPost-Quantum KEM Saber

Security

Hardware Security: Primitives, Architecture, Design & Test

Hosted in Virtual Platform

Research Manuscript

Optimizing ADC Utilization through Value-Aware Bypass in ReRAM-based DNN Accelerator

Design

AI/ML System Design

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Poster Networking Reception

Optimizing Fault Simulations with Formal Analysis for Asil Compliance

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

Optimizing hold eco using ML techniques

Presented In-Person

Networking Reception

Work-in-Progress Poster

Optimizing Temporal Convolutional Networks for Ultra-Low-Power Edge-Based Time Series Analytics

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Overlapping Checkers – A Better Substitute of End-to-End Checkers

Front-End Design

Hosted in Virtual Platform

Networking Reception

Work-in-Progress Poster

Parameter Approximation in CNNs for Improved Inference on FPGA

Presented In-Person

Research Manuscript

PAVFuzz: State-Sensitive Fuzz Testing of Protocols in Autonomous Vehicles

Autonomous Systems

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Presentations

PCI Express Specifications: Enabling Emerging Applications of Today and Tomorrow

Embedded Systems

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Presentations

Performance Modeling of Digital Processing Systems

Embedded Systems

Presented In-Person

Research Manuscript

Performance-Driven Simultaneous Partitioning and Routing for Multi-FPGA Systems

EDA

Physical Design and Verification, Lithography and DFM

Hosted in Virtual Platform

Research Manuscript

PETRI: Reducing Bandwidth Requirement in Smart Surveillance by Edge-Cloud Collaborative Adaptive Frame Clustering and Pipelined Bidirectional Tracking

Design

Design of Cyber-physical Systems and IoT

Hosted in Virtual Platform

Late Breaking Results Poster

Networking Reception

Physical Adversarial Attacks of Diffractive Deep Neural Networks

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

PI Signoff Methods Used in a 5nm InFO Design

Presented In-Person

Research Manuscript

PIM-Quantifier: A Processing-in-Memory Platform for mRNA Quantification

Embedded Systems

Near-Memory and In-Memory Computing

Hosted in Virtual Platform

Research Manuscript

PIMGCN: A ReRAM-Based PIM Design for Graph Convolutional Network Acceleration

Design

AI/ML System Design

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Poster Networking Reception

Pioneering Low Power Modeling and Verification Technique for custom blocks

Presented In-Person

Research Manuscript

PixelSieve: Towards Efficient Activity Analysis From Compressed Video Streams

Design

Approximate Computing for AI/ML

Hosted in Virtual Platform

Networking Reception

Work-in-Progress Poster

POSAR: A Flexible Posit Arithmetic Unit for RISC-V

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

Power Management Verification of AMD Radeon RX 5000 and RX 6000 Series GPUs

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Power Minimization for peak power and improved GPU sustainability

Front-End Design

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Presentations

Power Minimization of MCM/2.5D Chip-2-Chip communication interface

Front-End Design

Hosted in Virtual Platform

Tutorial

Practical Application of AI/ML to EDA Problems

EDA

Machine Learning/AI

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Practical Method for Clock Domain Crossing Using Simulation-Based Path Extraction

Front-End Design

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Poster Networking Reception

Predicting Timing Bottlenecks in Place & Route using Machine Learning

Presented In-Person

Research Manuscript

PrefixRL: Optimization of Parallel Prefix Circuits using Deep Reinforcement Learning

EDA

RTL/Logic Level and High-level Synthesis

Presented In-Person

Research Manuscript

PRID: Model Inversion Privacy Attacks in Hyperdimensional Learning Systems

Security

Hardware Security: Attack and Defense

Hosted in Virtual Platform

Research Manuscript

Prioritized Reinforcement Learning for Analog Circuit Optimization With Design Knowledge

EDA

Analog Design, Simulation, Verification and Test

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

Priority Synthesis in Physical Synthesis

Presented In-Person

Workshop

Privacy and Security by Design & Default: Understanding the Convergence of Law, Policy, and Technology

Presented In-Person

Special Session (Research Track)

Privacy-Preserving Medical Image Segmentation via Hybrid Trusted Execution Environment

Design

Machine Learning/AI

Hosted in Virtual Platform

Networking Reception

Work-in-Progress Poster

Procrastinating CFI for Hard Real-Time Systems

Presented In-Person

Special Session (Research Track)

Progress and Challenges of 3D Vision & Deep Learning in Industrial Robotics Application

Autonomous Systems

Machine Learning/AI

Hosted in Virtual Platform

Research Manuscript

Property-driven Automatic Generation of Reduced-ISA Hardware

EDA

System-on-Chip Design Methodology

Presented In-Person

Research Manuscript

PRUID: Practical User Interface Distribution for Multi-surface Computing

Embedded Systems

Embedded Software

Hosted in Virtual Platform

Research Manuscript

Pruning In Time (PIT): A Light-weight Network Architecture Optimizer for Temporal Convolutional Networks

Design

AI/ML System Design

Presented In-Person

Research Manuscript

Pruning of Deep Neural Networks for Fault-Tolerant Memristor-based Accelerators

EDA

Manufacturing Test and Reliability

Hosted in Virtual Platform

Research Manuscript

PSC-TG: RTL Power Side-Channel Leakage Assessment with Test Pattern Generation

Security

Hardware Security: Attack and Defense

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

PUF-based HRoT for Supply Chain Security

Hosted in Virtual Platform

Research Manuscript

QECOOL: On-Line Quantum Error Correction with a Superconducting Decoder for Surface Code

Design

Quantum Computing

Hosted in Virtual Platform

Research Manuscript

qSeq: Full Algorithmic and Tool Support for Synthesizing Sequential Circuits in Superconducting SFQ Technology

Design

Emerging Device Technologies

Presented In-Person

Research Manuscript

Quantifying Rowhammer Vulnerability for DRAM Security

EDA

Hardware Security: Attack and Defense

Hosted in Virtual Platform

Panel

Quantum Computing: An Industrial Perspective

Design

Quantum Computing

Hosted in Virtual Platform

Special Session (Research Track)

Quantum Random Access Coding in Quantum Machine Learning Applications

Design

Hosted in Virtual Platform

Research Manuscript

Quantum Spectral Clustering of Mixed Graphs

Design

Quantum Computing

Presented In-Person

Research Manuscript

RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU

Design

AI/ML System Design

Presented In-Person

Research Manuscript

RegHD: Robust and Efficient Regression in Hyper-Dimensional Learning System

Design

AI/ML System Design

Hosted in Virtual Platform

TechTalk

Reimagining Digital Simulation

Hosted in Virtual Platform

Presented In-Person

Tutorial

Reinforcement Learning in Digital System Simulation

Presented In-Person

Research Manuscript

Reinforcement Learning-Assisted Cache Cleaning to Mitigate Long-Tail Latency in DM-SMR

Embedded Systems

Embedded Memory, Storage and Networking

Hosted in Virtual Platform

Research Manuscript

RePIM: Joint Exploitation of Activation and Weight Repetition for In-ReRAM DNN Acceleration

Design

AI/ML System Design

Hosted in Virtual Platform

Research Manuscript

Reptail: Cutting Storage Tail Latency with Inherent Redundancy

Embedded Systems

Embedded System Design Methodologies

Hosted in Virtual Platform

Special Session (Research Track)

Requirement Specification, Analysis and Verification for Autonomous Systems

Autonomous Systems

Design

Hosted in Virtual Platform

Research Manuscript

Reversible Gating Architecture for Rare Failure Detection of Analog and Mixed-Signal Circuits

EDA

Manufacturing Test and Reliability

Presented In-Person

Research Manuscript

Rewrite to Reinforce: Rewriting the Binary to Apply Countermeasures against Fault Injection

Security

Embedded and Cross-Layer Security

Hosted in Virtual Platform

Networking Reception

Work-in-Progress Poster

RiSA: A Systolic Array Design Reinforced with Embedded Tensor Management and Accelerated Depthwise Convolutions

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

RISC-V processor verification methodology with dynamic testbench for asynchronous events

Presented In-Person

Research Manuscript

RL-Sizer: VLSI Gate Sizing for Timing Optimization using Deep Reinforcement Learning

EDA

Digital Design, Timing and Simulation

Presented In-Person

Research Manuscript

RoboRun: A Robot Runtime to Exploit Spatial Heterogeneity

Autonomous Systems

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Robust Timing Analysis And Optimization under Parametric On-Chip Process Variation

Presented In-Person

Research Manuscript

ROLoad: Securing Sensitive Operations with Pointee Integrity

Security

Embedded and Cross-Layer Security

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Poster Networking Reception

Root-cause analysis of undefined slack using timing/netlist data model

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Routability Improvement Methodology Using Multiple Standard Cells with Various Pin Location

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Routing layer re-optimization in Physical Synthesis

Back-End Design

Presented In-Person

Networking Reception

Work-in-Progress Poster

RTL regression test selection using Machine Learning

Presented In-Person

Research Manuscript

SACReD: An Attack Framework on SAC Resistant Delay-PUFs leveraging Bias and Reliability Factors

EDA

Hardware Security: Attack and Defense

Hosted in Virtual Platform

Special Session (Research Track)

Safety in Autonomous Driving: Can Tools Offer Guarantees?

Autonomous Systems

Design

Hosted in Virtual Platform

Research Manuscript

Scalable Pitch-Constrained Neural Processing Unit for 3D Integration with Event-Based Imagers

Design

Emerging Models of Computation

Presented In-Person

Research Manuscript

Scaling Deep-Learning Inference with Chiplet-based Architecture and Photonic Interconnects

Design

SoC, Heterogeneous, and Reconfigurable Architectures

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Scoring Vectors for IR Sign-off Using Power-Weighted Coverage Metrics

Front-End Design

Hosted in Virtual Platform

Research Manuscript

SEALing Neural Network Models in Encrypted Deep Learning Accelerators

Security

Hardware Security: Primitives, Architecture, Design & Test

Hosted in Virtual Platform

Research Manuscript

Secure Logic Locking with Strain-Protected Nanomagnet Logic

Design

Emerging Device Technologies

Presented In-Person

Networking Reception

Work-in-Progress Poster

Securing Deep Neural Networks Against Adversarial Attacks through Voltage Overscaling

Presented In-Person

Research Manuscript

Securing Hardware via Dynamic Obfuscation Utilizing Reconfigurable Interconnect and Logic Blocks

Security

Hardware Security: Primitives, Architecture, Design & Test

Hosted in Virtual Platform

Special Session (Research Track)

Security Primitives with Emerging Memories

Design

Security

Hosted in Virtual Platform

Research Manuscript

SeMPE: Secure Multi Path Execution Architecturefor Removing Conditional Branch Side Channels

Security

Embedded and Cross-Layer Security

Hosted in Virtual Platform

Research Manuscript

Sensitivity Importance Sampling Yield Analysis and Optimization for High Sigma Failure Rate Estimation

EDA

Manufacturing Test and Reliability

Hosted in Virtual Platform

Research Manuscript

SFLU: Synchronization-Free Sparse LU Factorization for Fast Circuit Simulation on GPUs

Embedded Systems

Near-Memory and In-Memory Computing

Hosted in Virtual Platform

Research Manuscript

SGL: Spectral Graph Learning from Measurements

EDA

Digital Design, Timing and Simulation

Hosted in Virtual Platform

Research Manuscript

SGX-FPGA: Trusted Execution Environment for CPU-FPGA Heterogeneous Architecture

Security

Embedded and Cross-Layer Security

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Poster Networking Reception

SHIFT LEFT: NOVEL POWER ANALYSIS METHOD for LARGE-SCALE AI PROCESSORS

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Shift-left Post-Silicon verification with Speed and Accuracy

Presented In-Person

Research Manuscript

SHORE: Hardware/Software Method for Memory Safety Acceleration on RISC-V

Security

Embedded and Cross-Layer Security

Hosted in Virtual Platform

Research Manuscript

Shortest Path to Secured Hardware: Domain Oriented Masking with High-Level-Synthesis

Security

Hardware Security: Primitives, Architecture, Design & Test

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Presentations

Signal Integrity aware HBM3 6.4Gbps interface Channel Optimization

Back-End Design

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Presentations

Silicon Debugging Using Function Failure Oriented Path Delay Fault Vectors

Back-End Design

Hosted in Virtual Platform

Networking Reception

Work-in-Progress Poster

SimpleChisel: A Hardware Design Language for Component-Level Heterogeneous Designs

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Simultaneous Design Methodology of High Speed & High Density Cell Libraries Using Two Different Rows in Single Design

Back-End Design

Hosted in Virtual Platform

Research Manuscript

Simultaneous Pre- and Free-assignment Routing for Multiple Redistribution Layers with Irregular Vias

EDA

Physical Design and Verification, Lithography and DFM

Hosted in Virtual Platform

Research Manuscript

Skew-oblivious Data Routing for Data Intensive Applications on FPGAs with HLS

Design

SoC, Heterogeneous, and Reconfigurable Architectures

Hosted in Virtual Platform

Research Manuscript

SLAP: A Supervised Learning Approach for Priority Cuts Technology Mapping

EDA

RTL/Logic Level and High-level Synthesis

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Smart digital sensors against tampering

Presented In-Person

Research Manuscript

SmartBoost: Lightweight ML-Driven Boosting for Thermally-Constrained Many-Core Processors

EDA

Cross-Layer Power Analysis and Low-Power Design

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

SoC Architectural Exploration for AI and ML accelerators with RISC-V

Embedded Systems

Presented In-Person

Research Manuscript

SoCCAR: Detecting SoC Security Violations Under Asynchronous Resets

EDA

Design Verification and Validation

Hosted in Virtual Platform

Research Manuscript

Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers

Design

Approximate Computing for AI/ML

Presented In-Person

Research Manuscript

SparkXD: A Framework for Resilient and Energy-Efficient Spiking Neural Network Inference using Approximate DRAM

Design

Emerging Models of Computation

Hosted in Virtual Platform

Additional Meeting

Designer, IP and Embedded Systems Track Presentations

Late Breaking Results Poster

Research Manuscript

Special Session (Research Track)

Tutorial

Work-in-Progress Poster

Speaker Office Hours

Presented In-Person

Networking Reception

Work-in-Progress Poster

SpecMCTS: Accelerating Monte Carlo Tree Search using Speculative Tree Traversal

Presented In-Person

Research Manuscript

SpikeDyn: A Framework for Energy-Efficient Spiking Neural Networks with Continual and Unsupervised Learning Capabilities in Dynamic Environments

Design

AI/ML System Design

Hosted in Virtual Platform

Research Manuscript

SPROUT - Smart Power ROUting Tool for Board-Level Exploration and Prototyping

EDA

Cross-Layer Power Analysis and Low-Power Design

Presented In-Person

Research Manuscript

SpV8: Pursuing Optimal Vectorization and Regular Computation Pattern in SpMV

Embedded Systems

Embedded Software

Hosted in Virtual Platform

Research Manuscript

ST2GPU: An Energy-Efficient GPU Design with Spatio-Temporal Shared-Thread Speculative Adders

EDA

Cross-Layer Power Analysis and Low-Power Design

Presented In-Person

Research Manuscript

Statheros: Compiler for Efficient Low-Precision Probabilistic Programming

Design

Approximate Computing for AI/ML

Presented In-Person

Networking Reception

Work-in-Progress Poster

Stimulus Truncation Method for Energy Efficient Memristor Based Neuromorphic Computing

Presented In-Person

Research Manuscript

StocHD: Stochastic Hyperdimensional System for Efficient and Robust Learning from Raw Data

Design

SoC, Heterogeneous, and Reconfigurable Architectures

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Presentations

Strategy for Mixed Signal IP Integration to Accelerate High-Quality SOC Development

Hosted in Virtual Platform

Research Manuscript

Subresolution Assist Feature Insertion by Variational Adversarial Active Learning and Clustering with Data Point Retrieval

EDA

Physical Design and Verification, Lithography and DFM

Hosted in Virtual Platform

Research Manuscript

Synergically Rebalancing Parallel Execution via DCT and Turbo Boosting

EDA

Cross-Layer Power Analysis and Low-Power Design

Presented In-Person

Research Manuscript

Synthesizing Barrier Certificates of Neural Network Controlled Continuous Systems via approximations

EDA

Design Verification and Validation

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Presentations

Systematic Generation and Refresh of Standard Cell Abutment Database

Back-End Design

Hosted in Virtual Platform

Special Session (Research Track)

TACOS: Tactile Core with Optical String Sensor for Robotic Smart Skin

Autonomous Systems

Machine Learning/AI

Hosted in Virtual Platform

Research Manuscript

TAIT: One-Shot Full-Integer Lightweight DNN Quantization via Tunable Activation Imbalance Transfer

Design

AI/ML System Design

Hosted in Virtual Platform

Research Manuscript

Tamper-Resistant Optical Logic Circuits Based on Integrated Nanophotonics

Design

Emerging Device Technologies

Hosted in Virtual Platform

Networking Reception

Work-in-Progress Poster

Tapeout of a RISC-V Crypto Chip with Hardware Trojans: A Case-Study on Trojan Design and Pre-Silicon Detectability

Presented In-Person

Research Manuscript

TARe: Task-Adaptive in-situ ReRAM Computing for Graph Learning

Design

AI/ML System Design

Hosted in Virtual Platform

Networking Reception

Work-in-Progress Poster

Tatami: Dynamic CGRA Reconfiguration for Multi-Core General Purpose Processing

Presented In-Person

Research Manuscript

TCL: an ANN-to-SNN Conversion with Trainable Clipping Layers

Design

Approximate Computing for AI/ML

Presented In-Person

Research Manuscript

TensorLib: A Spatial Accelerator Generation Framework for Tensor Algebra

EDA

RTL/Logic Level and High-level Synthesis

Hosted in Virtual Platform

TechTalk

The AI hype cycle is over. Now what?

Hosted in Virtual Platform

Presented In-Person

Special Session (Research Track)

The Current State of TinyML – Opportunities, Challenges and the Road Ahead

Embedded Systems

Machine Learning/AI

Hosted in Virtual Platform

Keynote

The Potential of Machine Learning for Hardware Design

Hosted in Virtual Platform

Presented In-Person

Analyst Review

The State of EDA: A View from Wall Street

Hosted in Virtual Platform

Presented In-Person

Research Manuscript

Theory-Specific Proof Steps Witnessing Correctness of SMT Executions

EDA

Design Verification and Validation

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Thermal-aware SOC floorplanning method based on a customized Deep-Q Network algorithm

Back-End Design

Hosted in Virtual Platform

Special Session (Research Track)

tinyML on embedded microprocessors and the broad avenue of opportunities

Embedded Systems

Machine Learning/AI

Hosted in Virtual Platform

Research Manuscript

Topology Agnostic Virtual Channel Assignment and Protocol Level Deadlock Avoidance in a Network-on-Chip

EDA

In-Package and On-Chip Communication and Networks-on-Chip

Presented In-Person

Networking Reception

Work-in-Progress Poster

Towards Deploying PSS to Early Design Space Exploration

Presented In-Person

Special Session (Research Track)

Towards Fully Intelligent Transportation through Infrastructure-Vehicle Cooperative Autonomous Driving: Challenges and Opportunities

Autonomous Systems

Design

Hosted in Virtual Platform

Research Manuscript

Towards Improving the Trustworthiness of Hardware based Malware Detector using Online Uncertainty Estimation

Security

Embedded and Cross-Layer Security

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Towards measuring layout pattern coverage: a Machine Learning Approach

Presented In-Person

Research Manuscript

Towards Reliable Spatial Memory Safety for Embedded Software by Combining Checked C with Concolic Testing

Embedded Systems

Embedded Software

Hosted in Virtual Platform

Research Manuscript

Towards Resilient Deployment of In-Memory Neural Networks with High Throughput

Design

AI/ML System Design

Presented In-Person

Research Manuscript

Training Acceleration for Deep Neural Networks: A Hybrid Parallelization Strategy

Embedded Systems

Time-Critical System Design

Hosted in Virtual Platform

DAC Pavilion Panels

Trust and verify. Overcoming costly and piecemeal approaches to pre-silicon side-channel attack vulnerability analysis and verification

Presented In-Person

Research Manuscript

Trust-Region Method with Deep Reinforcement Learning in Analog Design Space Exploration

EDA

Analog Design, Simulation, Verification and Test

Hosted in Virtual Platform

Research Manuscript

Ultra-Fast CGRA Scheduling to Enable Run Time, Programmable CGRAs

Design

SoC, Heterogeneous, and Reconfigurable Architectures

Presented In-Person

Research Manuscript

Ultrafast CPU/GPU Kernels for Density Accumulation in Placement

EDA

Physical Design and Verification, Lithography and DFM

Hosted in Virtual Platform

Research Manuscript

UMOC: Unified Modular Ordering Constraints to Unify Cycle- and Register-Transfer-Level Modeling

EDA

RTL/Logic Level and High-level Synthesis

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Unified FW/ASIC Co-Simulation for Earlier and Accelerated Pre-Silicon Testing

Front-End Design

Hosted in Virtual Platform

Research Manuscript

Universal Symmetry Constraint Extraction for Analog and Mixed-Signal Circuits with Graph Neural Networks

EDA

Analog Design, Simulation, Verification and Test

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

Updating RISC-V microarchitecture in the field through Menta co-extended cores and Codasip Studio

Presented In-Person

Research Manuscript

UPTPU: Improving Energy Efficiency of a Tensor Processing Unit through Underutilization Based Power-Gating

EDA

System-on-Chip Design Methodology

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Using Clock Skew to Fix Hold: A Path-Depth Based Useful-Skew Approach to Reduce Hold Buffer Insertion

Back-End Design

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

Utilizing the Cloud to Increase Library Characterization Throughput and Reduce Schedule Bottlenecks

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

UVM is 10 Years Old: What's Next?

Front-End Design

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

UVM: Where the Wild Things Are

Front-End Design

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

Verification Methodology for High Resolution High Speed CMOS Image Sensor SoC - Leveraging Innovations in EDA Tools

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Verifying Reset and Power Domains Together

Front-End Design

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Presentations

Virtual Environment for Developing Reinforcement Learning and Its application for thermal management

Back-End Design

Hosted in Virtual Platform

Special Session (Research Track)

Vision of Automating the Implementation of Security into Silicon

Security

Hosted in Virtual Platform

Presented In-Person

Research Manuscript

VLSI Structure-aware Placement for Convolutional Neural Network Accelerator Units

EDA

Physical Design and Verification, Lithography and DFM

Hosted in Virtual Platform

Networking Reception

Welcome Reception

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

What can chip design learn from the software world?

Machine Learning/AI

Hosted in Virtual Platform

Keynote

When the Winds of Change Blow, Some People Build Walls and Others Build Windmills

Hosted in Virtual Platform

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

WOW: Approximate WOrkload Watcher

Front-End Design

Hosted in Virtual Platform

Networking Reception

Work-in-Progress Poster

ZEM: Zero-cycle Bit-masking Module for Deep Learning Refresh-less DRAM

Presented In-Person

Research Manuscript

ZeroBN: Learning Compact Neural Networks For Latency-Critical Edge Systems

Embedded Systems

Embedded System Design Methodologies

Hosted in Virtual Platform

Sessions

Research Manuscript

2021: A Space Odyssey in Place and Route

EDA

Physical Design and Verification, Lithography and DFM

Hosted in Virtual Platform

Research Manuscript

A Melange of Machine Learning Frameworks for Optimization

Design

AI/ML System Design

Presented In-Person

Research Manuscript

A Melange of Machine Learning Frameworks for Optimization

Design

AI/ML System Design

Hosted in Virtual Platform

Special Session (Research Track)

A Quantum Leap in Machine Learning: From Applications to Implementations

Design

Hosted in Virtual Platform

Research Manuscript

A-Eye on the Cutting Edge of IoT

Embedded Systems

Embedded System Design Methodologies

Hosted in Virtual Platform

Research Manuscript

A-Eye on the Cutting Edge of IoT

Embedded Systems

Embedded System Design Methodologies

Presented In-Person

Special Session (Research Track)

Accelerating EDA Algorithms with GPUs and Machine Learning

EDA

Machine Learning/AI

Hosted in Virtual Platform

Presented In-Person

Special Session (Research Track)

Accelerating EDA Algorithms with GPUs and Machine Learning

EDA

Hosted in Virtual Platform

Research Manuscript

AIVengers: Emerging AI Algorithms to the Rescue

Design

AI/ML System Design

Hosted in Virtual Platform

Research Manuscript

AIVengers: Emerging AI Algorithms to the Rescue

Design

AI/ML System Design

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

All Routes Lead to Closing Timing

Back-End Design

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Presentations

All Routes Lead to Closing Timing

Back-End Design

Presented In-Person

Research Manuscript

An Approximate World from Neurons to Genomes

Design

Approximate Computing for AI/ML

Presented In-Person

Research Manuscript

An Approximate World from Neurons to Genomes

Design

Approximate Computing for AI/ML

Hosted in Virtual Platform

Training Day

Anatomy of an Embedded Linux System & User/Kernel Debug

Design

Embedded Systems

Hosted in Virtual Platform

Research Manuscript

Automating Autonomy: From GPU to Traffic Control

Autonomous Systems

Presented In-Person

Research Manuscript

Automating Autonomy: From GPU to Traffic Control

Autonomous Systems

Hosted in Virtual Platform

Keynote

Awards and Tuesday Keynote

Hosted in Virtual Platform

Presented In-Person

Keynote

Awards and Wednesday Keynote

Hosted in Virtual Platform

Presented In-Person

Research Manuscript

Beyond Supervised Learning: Approaches for Efficient and Reliable Intelligence

Design

AI/ML System Design

Presented In-Person

Research Manuscript

Beyond Supervised Learning: Approaches for Efficient and Reliable Intelligence

Design

AI/ML System Design

Hosted in Virtual Platform

Research Manuscript

Big Data into Small Devices

Embedded Systems

Embedded Software

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Presentations

Chip Design and Cloud: the Good, the Emerging, and the Potential

Cloud

Presented In-Person

Research Manuscript

Critical Design for Timing Critical Systems

Embedded Systems

Time-Critical System Design

Presented In-Person

Research Manuscript

Critical Design for Timing Critical Systems

Embedded Systems

Time-Critical System Design

Hosted in Virtual Platform

Keynote

DAC Best Paper & Presentation Awards & Thursday Keynote

Hosted in Virtual Platform

Presented In-Person

Research Manuscript

Deep Learn your Yield

EDA

Physical Design and Verification, Lithography and DFM

Presented In-Person

Research Manuscript

Deep Learn Your Yield

EDA

Physical Design and Verification, Lithography and DFM

Hosted in Virtual Platform

Training Day

Deep Learning for Electronic Engineers

Machine Learning/AI

Hosted in Virtual Platform

Special Session (Research Track)

Democratizing Design Automation: Next Generation Opensource Tools for Hardware Specialization

EDA

Machine Learning/AI

Hosted in Virtual Platform

Special Session (Research Track)

Design Automation of Autonomous Systems: State-of-the-Art and Future Directions

Autonomous Systems

Design

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Poster Networking Reception

Designer, IP and Embedded Systems Poster Networking Reception

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

Presented In-Person

Designer, IP and Embedded Systems Track Poster Networking Reception

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Designer, IP, and Embedded Systems Poster Gladiators Presentation

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Designer, IP, and Embedded Systems Poster Gladiators Presentation

Presented In-Person

Research Manuscript

Designers Relax: Generating Analog with a Click

Design

Digital and Analog Circuits

Hosted in Virtual Platform

Analyst Review

Digitalization—the return to outsize growth for the semiconductor industry

Hosted in Virtual Platform

Presented In-Person

Research Manuscript

Dirty Tricks on Embedded Systems

Embedded Systems

Embedded Software

Hosted in Virtual Platform

Research Manuscript

Embedded Recipes for Secure and Bug-Free Soups

Security

Embedded and Cross-Layer Security

Presented In-Person

Research Manuscript

Embedded Recipes for Secure and Bug-Free Soups

Security

Embedded and Cross-Layer Security

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Presentations

Embedded Systems! Projects and Solutions

Embedded Systems

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Presentations

Embedded Systems! Projects and Solutions

Embedded Systems

Presented In-Person

Panel

Environmentally-Sustainable Computing

Design

Hosted in Virtual Platform

Presented In-Person

Research Manuscript

Exploit your modules for complete verification

EDA

Design Verification and Validation

Presented In-Person

Research Manuscript

Exploit your modules for complete verification

EDA

Design Verification and Validation

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Presentations

Exploring the New Waves

Back-End Design

Hosted in Virtual Platform

Research Manuscript

Fantastic SoCs and Where to Find Them!

EDA

System-on-Chip Design Methodology

Presented In-Person

Research Manuscript

Fantastic SoCs and Where to Find Them!

EDA

System-on-Chip Design Methodology

Hosted in Virtual Platform

Research Manuscript

Fast, Cool and Error Tolerant Compute-In-Memory

Embedded Systems

Near-Memory and In-Memory Computing

Hosted in Virtual Platform

Research Manuscript

Fast, Cool and Error Tolerant Compute-In-Memory

Embedded Systems

Near-Memory and In-Memory Computing

Presented In-Person

Research Manuscript

From Brains to Bits

Design

Emerging Models of Computation

Presented In-Person

Research Manuscript

From Brains to Bits

Design

Emerging Models of Computation

Hosted in Virtual Platform

Additional Meeting

HACK@DAC

Presented In-Person

Special Session (Research Track)

Hardware Aware Learning for Medical Image Computing and Computer Assisted Intervention

Design

Machine Learning/AI

Hosted in Virtual Platform

Panel

Homomorphic Computing as a foundational technology: Theory, Practice, and Future Business

Security

Hosted in Virtual Platform

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Innovative Solutions for Simulation and Registers

Front-End Design

Hosted in Virtual Platform

Research Manuscript

Intelligent Edge-Cloud Computing Architectures for CPS

Design

Design of Cyber-physical Systems and IoT

Presented In-Person

Research Manuscript

Intelligent Edge-Cloud Computing Architectures for CPS

Design

Design of Cyber-physical Systems and IoT

Hosted in Virtual Platform

Research Manuscript

Intelligent Software and System Architectures for Smart Memories

Embedded Systems

Near-Memory and In-Memory Computing

Presented In-Person

Research Manuscript

Intelligent Software and System Architectures for Smart Memories

Embedded Systems

Near-Memory and In-Memory Computing

Hosted in Virtual Platform

Designer, IP and Embedded Systems Track Presentations

Is Your Product Secure? - An IP Driven Approach to Product Security

Presented In-Person

Designer, IP and Embedded Systems Track Presentations

Is Your Product Secure? - An IP Driven Approach to Product Security

Hosted in Virtual Platform

Research Manuscript

Keep Your Secrets Safe: Side-channel Attacks and Assessment techniques

Security

Hardware Security: Attack and Defense

Hosted in Virtual Platform

Research Manuscript

Keep Your Secrets Safe: Side-channel Attacks and Assessment techniques

Security

Hardware Security: Attack and Defense

Presented In-Person

Late Breaking Results Poster

Networking Reception

Late Breaking Results Posters & Networking Reception

Presented In-Person

Research Manuscript

Learn to Design better NoC

EDA

In-Package and On-Chip Communication and Networks-on-Chip

Presented In-Person

Research Manuscript

Learn to Design better NoC

EDA

In-Package and On-Chip Communication and Networks-on-Chip

Hosted in Virtual Platform

Research Manuscript

Learning to Accelerate Circuit Timing Analysis

EDA

Digital Design, Timing and Simulation

Presented In-Person

Research Manuscript

Learning to Accelerate Circuit Timing Analysis

EDA

Digital Design, Timing and Simulation

Hosted in Virtual Platform

Research Manuscript

Let There Be Light: Emerging Technology for Intelligent Systems

Design

AI/ML System Design

Hosted in Virtual Platform

Research Manuscript

Let There Be Light: Emerging Technology for Intelligent Systems

Design

AI/ML System Design

Presented In-Person

Research Manuscript

Locks, Clones and Hammers: Trusting your chip in a vulnerable world

Security

Hardware Security: Attack and Defense

Presented In-Person

Research Manuscript

Locks, Clones and Hammers: Trusting your chip in a vulnerable world

EDA

Hardware Security: Attack and Defense

Hosted in Virtual Platform

Research Manuscript

Logic Synthesis got even better. Can you believe it? Machine learning to the rescue

EDA

RTL/Logic Level and High-level Synthesis