Research Manuscript: Logic Synthesis got even better. Can you believe it? Machine learning to the rescue
Event TypeResearch Manuscript
RTL/Logic Level and High-level Synthesis
TimeWednesday, December 8th3:30pm - 5:00pm PST
DescriptionThe use of machine learning in EDA is deeply impacting the field. In this session we show how machine learning (ML) techniques are used to improve logic synthesis. The first paper uses reinforcement learning to design parallel prefix circuits such as adders and priority encoders that are fundamental in high-performance circuits, while the second paper uses ML to develop a novel technology mapping algorithm. The third paper proposes a framework to generate hardware accelerators for tensor algebra application. The next paper applies FPGA-based synthesis methods to ASIC synthesis. Finally, the last two papers present methods to efficient simulate complex problems. In particular the tight integration between the circuit simulation and a Boolean satisfiability solver, and a cycle-accurate simulation models with RTL models.