Designer, IP and Embedded Systems Track Presentations: New Frontiers in Formal and Static Verification
Event TypeDesigner, IP and Embedded Systems Track Presentations
Virtual Programs
Presented In-Person
Front-End Design
TimeTuesday, December 7th10:30am - 11:30am PST
DescriptionIn this essential session, there will be talks that focus on new explorations of formal techniques and tools by industry giants and research lab. A new approach to use formal analysis to ensure automotive SoC’s adhere to safety standards will be presented. Other presentations focus on architectural analysis, design partitioning and completeness for formal sign-off. Finally, a couple of presentations focus on static verification techniques for reset/power domains and constraint based clock-domain crossing sign-off that circumvent error-prone waiver mechanism.