Session
Designer, IP and Embedded Systems Track Presentations: New Frontiers in Formal and Static Verification
Session Chair
Event TypeDesigner, IP and Embedded Systems Track Presentations
Virtual Programs
Presented In-Person
Topics
Front-End Design
Location2010/2012
DescriptionIn this essential session, there will be talks that focus on new explorations of formal techniques and tools by industry giants and research lab. A new approach to use formal analysis to ensure automotive SoC’s adhere to safety standards will be presented. Other presentations focus on architectural analysis, design partitioning and completeness for formal sign-off. Finally, a couple of presentations focus on static verification techniques for reset/power domains and constraint based clock-domain crossing sign-off that circumvent error-prone waiver mechanism.
Presentations
10:30am - 10:37am PST | Optimizing Fault Simulations with Formal Analysis for Asil Compliance | ![]() ![]() | |
10:37am - 10:45am PST | Constraints based CDC Sign-Off methodology | ![]() ![]() | |
11:15am - 11:22am PST | MOVE TO VIRTUAL: LabReplay: Efficient Replay of Post-Silicon Debug for High Performance Microprocessor Designs | ![]() ![]() | |
11:22am - 11:30am PST | Ensuring Completeness of Formal Verification with GapFree: Are we done yet? Presenter(s) | Hosted in Virtual Platform | ![]() ![]() |