Event TypeDesigner, IP and Embedded Systems Track Presentations
TimeTuesday, December 7th10:30am - 11:30am PST
DescriptionDoes a solid design in itself guarantee solid end product? With SOC Design methodologies well understood, often times teams face challenges in terms of having robust Silicon due to power/performance, test coverage and reliability related issues. In this session, experts will talk about some of the key factors that can be considered during design phase of the Chip to solidify the Silicon. We will look at techniques used by some of the experienced engineers to improve effects of aging and reduce variability challenges, ways to improve power and performance of your designs and key considerations while integrating Mixed-Signal IPs.