Networking Reception, Work-in-Progress Poster: Networking Reception & Work-In-Progress Poster Session
Event TypeNetworking Reception, Work-in-Progress Poster
Virtual Programs
Presented In-Person
TimeTuesday, December 7th6:00pm - 7:00pm PST
LocationLevel 2 - Lobby
Ambrosia: Reduction in Data Transfer from Sensor to Server for Increased Lifetime of IoT Sensor Nodes
Context-Aware Task Handling in Resource-Constrained Robots with Virtualization
CoDR: Computation and Data Reuse Aware CNN Accelerator
DeltaNet: High-Performance Federated Learning with Hybrid Data & Model Parallelism
Design Context Aware Electromigration Analysis Methodology to Overcome BEOL Interconnect Scaling Induced Reliability Risk for Advanced Process Technology
Detecting security and privacy threats in home IoT networks through traffic profiling
EdgenAI: Distributed Inference with Local Edge Devices and Minimum Latency
Efficient Real-Time Object Detection with Adaptive Image Scaling and Cropping
Energy Harvesting Aware Multi-hop Routing and Energy Allocation in Distributed IoT System based on Multi-agent Reinforcement Learning
Guiding Global Placement with Reinforcement Learning
HammerFilter: Robust Protection and Low Hardware Overhead Method for Row-Hammering
A High Efficiency Power Obfuscation Switched Capacitor DC-DC Converter Architecture
An In-Memory Analog Computing Co-Processor for Energy-Efficient CNN Inference on Mobile Devices
Learning Quantum Circuit Errors Based on Error Propagation
Novel Static Timing Analysis considering Dynamic Voltage Drop
Optimizing Temporal Convolutional Networks for Ultra-Low-Power Edge-Based Time Series Analytics
Procrastinating CFI for Hard Real-Time Systems
RiSA: A Systolic Array Design Reinforced with Embedded Tensor Management and Accelerated Depthwise Convolutions
CANCELLED: RVfplib: A Fast and Compact Open-Source Floating-Point Emulation Library for Tiny RISC-V Processors
SimpleChisel: A Hardware Design Language for Component-Level Heterogeneous Designs
Tapeout of a RISC-V Crypto Chip with Hardware Trojans: A Case-Study on Trojan Design and Pre-Silicon Detectability
Towards Deploying PSS to Early Design Space Exploration
ZEM: Zero-cycle Bit-masking Module for Deep Learning Refresh-less DRAM