Designer, IP and Embedded Systems Track Poster Networking Reception: Designer, IP and Embedded Systems Track Poster Networking Reception
Event TypeDesigner, IP and Embedded Systems Track Poster Networking Reception
Virtual Programs
Presented In-Person
TimeTuesday, December 7th5:00pm - 6:00pm PST
LocationLevel 2 - Exhibit Hall
Aging Timing Analysis Based on EMPYREAN-XTime
Analog in memory computing optimization with TOPS/W Methodology
Andes ACE feature extended on Menta eFPGA for RISC-V cores ISA reconfigurability in the field
An Automated Approach to Pre-empt Clock-Divergence & Achieve Predictable Timing Closure
Automated Generation of Current Controlled Oscillator (CCO) Layout using Template Reuse Flow
Constraints based CDC Sign-Off methodology
Deep data for faster silicon bring-up, characterization, and qualification with higher confidence
Dual Feature Vector Hetero Graph Neural Network (DFV-GNN) based Post-Layout Parasitic Estimation
Efficient Impedance Discontinuity Optimization Technique for High Speed Interfaces
Embedded Security optimized with eFPGA
Ensuring Completeness of Formal Verification with GapFree: Are we done yet?
Hosted in Virtual Platform
Extended Power Connectivity Solution for CPF based Low Power Simulation
Formal Verification of Safety Mechanisms | Infineon Technologies
A Highly Reusable Generic UVM for Soft Processors
MOVED TO VIRTUAL: Innovative In-Situ Slack Monitor (IS2M) Design for Dynamic Detection of Voltage Temperature Ageing Change.
Mitigating Variability Challenges of IPs for Robust Design
Novel Chip-Package-System Power Noise Analysis with RTL Power Profiling
On the Energy Efficiency of Machine Learning Frameworks
"OpenOPU" , A Complete Solution for Heterogeneous Computing
Optimizing Fault Simulations with Formal Analysis for Asil Compliance
Power Management Verification of AMD Radeon RX 5000 and RX 6000 Series GPUs
Routability Improvement Methodology Using Multiple Standard Cells with Various Pin Location
CANCELLED: A Single Solution for Scanning, Tracking Inventory, Transactions, and Recharging
A Scalable Multicore RISC-V GPGPU Accelerator for High-End FPGAs
Abstraction- An efficient methodology for RTL & Low-Power Signoff in SoC Design
Towards measuring layout pattern coverage: a Machine Learning Approach