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DTSTAMP:20211208T164507Z
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DTSTART;TZID=America/Los_Angeles:20211209T153000
DTEND;TZID=America/Los_Angeles:20211209T170000
UID:dac_DAC 2021_sess104@linklings.com
SUMMARY:Reconfigurability across the Spectrum: From ICs to Intelligence
DESCRIPTION:Research Manuscript\n\nReconfigurability has become essential,
  for efficient processing at all layers of the compute stack. This session
  presents novel architectures for integrating thousands of cores on a sing
 le wafer, as well as interconnect technologies for 3D integration. Moreove
 r, architectures for emerging AI paradigms such as hyper-dimensional compu
 ting and graph neural networks are presented. Finally, ultra-fast reconfig
 uration techniques for CGRAs and for virtualizing FPGAs are discussed.\n\n
 Designing a 2048-Chiplet, 14336-Core Waferscale Processor\n\nPal\n\nWafers
 cale processor systems can provide a large number of cores, memory capacit
 y and bandwidth required by today's highly parallel workloads. One approac
 h to building waferscale systems is to use a chiplet-based approach where 
 pre-tested chiplets are integrated on a passive silicon-interconnect waf..
 .\n\n---------------------\nUltra-Fast CGRA Scheduling to Enable Run Time,
  Programmable CGRAs\n\nLee\n\nCoarse-Grained Reconfigurable Arrays (CGRAs)
  offer the potential for both energy-efficiency and high-throughput in emb
 edded systems today. One limitation of CGRAs is the extremely long mapping
  time that can take many hours to complete. This, coupled with static prog
 ramming, limits the number of kern...\n\n---------------------\nMicro-bump
 ing, Hybrid Bonding, or Monolithic? A PPA Study for Heterogeneous 3D IC Op
 tions\n\nKim\n\nIn this paper, we present three commercial-grade 3D IC des
 igns based on state-of-the-art design technologies, specifically micro-bum
 ping (3D die stacking), hybrid bonding (wafer-on-wafer bonding) and monoli
 thic 3D IC (M3D). To highlight trade-offs present in these three designs, 
 we perform analyses ...\n\n\nTopic: Design\n\nKeyword: SoC, Heterogeneous,
  and Reconfigurable Architectures\n\nVirtual Program: Presented In-Person
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