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DTSTAMP:20211208T164414Z
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DTSTART;TZID=America/Los_Angeles:20211209T153000
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UID:dac_DAC 2021_sess104_RESEARCH238@linklings.com
SUMMARY:Designing a 2048-Chiplet, 14336-Core Waferscale Processor
DESCRIPTION:Research Manuscript\n\nDesigning a 2048-Chiplet, 14336-Core Wa
 ferscale Processor\n\nPal\n\nWaferscale processor systems can provide a la
 rge number of cores, memory capacity and bandwidth required by today's hig
 hly parallel workloads. One approach to building waferscale systems is to 
 use a chiplet-based approach where pre-tested chiplets are integrated on a
  passive silicon-interconnect wafer. This technology allows heterogeneous 
 integration and can provide significant performance and cost benefits. How
 ever, designing such a waferscale system has several challenges such as po
 wer delivery, clock distribution, waferscale-network design, design for te
 stability and fault-tolerance. In this work, we discuss these challenges a
 nd the design solutions we employed to build a 2048-chiplet, 14336-core wa
 ferscale processor prototype.\n\nTopic: Design\n\nKeyword: SoC, Heterogene
 ous, and Reconfigurable Architectures\n\nVirtual Program: Presented In-Per
 son
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