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DTSTAMP:20211208T164414Z
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DTSTART;TZID=America/Los_Angeles:20211209T160000
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UID:dac_DAC 2021_sess104_RESEARCH784@linklings.com
SUMMARY:Micro-bumping, Hybrid Bonding, or Monolithic? A PPA Study for Hete
 rogeneous 3D IC Options
DESCRIPTION:Research Manuscript\n\nMicro-bumping, Hybrid Bonding, or Monol
 ithic? A PPA Study for Heterogeneous 3D IC Options\n\nKim\n\nIn this paper
 , we present three commercial-grade 3D IC designs based on state-of-the-ar
 t design technologies, specifically micro-bumping (3D die stacking), hybri
 d bonding (wafer-on-wafer bonding) and monolithic 3D IC (M3D). To highligh
 t trade-offs present in these three designs, we perform analyses on power,
  performance, and area and the clock tree. We also model the tier-to-tier 
 interconnection in each 3D IC methodology and analyze signal integrity to 
 assess the reliability of each design. From our experiments, hybrid bondin
 g design shows the best timing improvement of 81.4% when compared to its 2
 D counterpart, while micro-bumping shows the best reliability among 3D IC 
 designs.\n\nTopic: Design\n\nKeyword: SoC, Heterogeneous, and Reconfigurab
 le Architectures\n\nVirtual Program: Presented In-Person
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