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DTSTART:19700308T020000
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DTSTAMP:20211208T164507Z
LOCATION:3016
DTSTART;TZID=America/Los_Angeles:20211208T143500
DTEND;TZID=America/Los_Angeles:20211208T150000
UID:dac_DAC 2021_sess129@linklings.com
SUMMARY:Learning to Accelerate Circuit Timing Analysis
DESCRIPTION:Research Manuscript\n\nThis session presents advanced methods 
 for circuit timing analysis and optimization. The first two papers use new
  algorithms, data structures, and machine-level optimizations for improvin
 g the efficiency of common path pessimism removal (CPPR) problem and path-
 based timing analysis. The last two papers use machine learning techniques
  for learning resistor networks from linear measurements and for gate sizi
 ng.\n\nRL-Sizer: VLSI Gate Sizing for Timing Optimization using Deep Reinf
 orcement Learning\n\nLu\n\nGate sizing for timing optimization is performe
 d extensively throughout Electronic Design Automation (EDA) flows. However
 , existing algorithms in commercial tools heavily rely on meta-heuristics 
 which lead to sub-optimal sizing solutions. Reinforcement Learning (RL) is
  a disruptive paradigm that ach...\n\n\nTopic: EDA\n\nKeyword: Digital Des
 ign, Timing and Simulation\n\nVirtual Program: Presented In-Person
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