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DTSTAMP:20211208T164507Z
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DTSTART;TZID=America/Los_Angeles:20211208T103000
DTEND;TZID=America/Los_Angeles:20211208T113000
UID:dac_DAC 2021_sess132@linklings.com
SUMMARY:Exploit your modules for complete verification
DESCRIPTION:Research Manuscript\n\nThis session presents innovations that 
 can boost effectiveness, specificity, automation, and confidence in module
 -level verification. It contributes an efficient test-generation algorithm
  for dynamic verification of DRAMs based on deep reinforcement learning an
 d a method based on graybox fuzzing for effective and rapid test generatio
 n targeting specific module instances in large RTL designs. The session th
 en proceeds with a tool for automatically constructing formal testbenches 
 using SystemVerilog assertions to aid verification of the control logic go
 verning the interactions between design modules. Finally, it offers a syst
 em for efficiently certifying the correctness of first-order logic proofs 
 in satisfiability modulo theories solvers.\n\nTheory-Specific Proof Steps 
 Witnessing Correctness of SMT Executions\n\nHyvärinen\n\nEnsuring hardware
  and software correctness increasingly relies on the use of symbolic logic
  solvers, in particular for satisfiability modulo theories (SMT).  However
 , building efficient and correct SMT solvers is difficult: even state-of-t
 he-art solvers disagree on instance satisfiability.  This wor...\n\n------
 ---------------\nAutoSVA: Democratizing Formal Verification of RTL Module 
 Interactions\n\nOrenes-Vera\n\nModern SoC design relies on the ability to 
 separately verify IP blocks relative to their own specifications. Formal v
 erification (FV) using SystemVerilog Assertions (SVA) is an effective meth
 od to exhaustively verify blocks at unit-level. Unfortunately, FV has a st
 eep learning curve and requires eng...\n\n\nTopic: EDA\n\nKeyword: Design 
 Verification and Validation\n\nVirtual Program: Presented In-Person
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