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DTSTAMP:20211208T164410Z
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DTSTART;TZID=America/Los_Angeles:20211208T113000
DTEND;TZID=America/Los_Angeles:20211208T115200
UID:dac_DAC 2021_sess133_RESEARCH1096@linklings.com
SUMMARY:ISA Modeling with Trace Notation for Context Free Property Generat
 ion
DESCRIPTION:Research Manuscript\n\nISA Modeling with Trace Notation for Co
 ntext Free Property Generation\n\nDevarajegowda\n\nThe  scalable  and  ext
 endable  RISC-V  ISA introduced  a  new  level  of  flexibility  in embedd
 ed  processor  design.  However,  the  required  modeling and  verificatio
 n  expertise  are  the  major  hurdles  in leveraging  the flexibility  pr
 ovided  by  the  ISA.  Formal verification is increasingly used for design
  verification and the properties are manually written or partially generat
 ed. Additional microarchitectural details are added manually, thus increas
 ing the efforts needed.\nWe  propose a trace notation for ISA definition t
 o capture the implicit execution behavior of a processor. The trace notati
 on is annotated with timing and hierarchy information to adapt the trace t
 o any kind of processor architecture.\n\nTopic: EDA\n\nKeyword: Design Ver
 ification and Validation\n\nVirtual Program: Presented In-Person
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