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DTSTAMP:20211208T164509Z
LOCATION:3014
DTSTART;TZID=America/Los_Angeles:20211209T110000
DTEND;TZID=America/Los_Angeles:20211209T120000
UID:dac_DAC 2021_sess159@linklings.com
SUMMARY:A Melange of Machine Learning Frameworks for Optimization
DESCRIPTION:Research Manuscript\n\nThe landscape of machine learning syste
 ms is evolving very fast, and many optimizations are needed across algorit
 hm, compiler, and hardware accelerator designs. In this session, we highli
 ght frameworks for machine learning system optimization covering four topi
 cs: memory-efficient graph neural network design, neural hardware-compiler
  co-design, energy-efficient unsupervised spiking neural network framework
 , and Bayesian neural network hardware accelerator.\n\nEvolved Neural-Hard
 ware-Compiler Co-Design\n\nLin\n\nHardware architecture search is an effic
 ient tool to enable specialized accelerator designs for neural networks. C
 urrent search frameworks focus on sizing the architectural hyper-parameter
 s while neglect searching the PE connectivity and compiler mappings.\nTo t
 ackle this challenge, we propose ENHCS ...\n\n---------------------\nHigh-
 Performance FPGA-based Accelerator for Bayesian Neural Networks\n\nFerianc
 \n\nIn this work, we propose a novel FPGA-based hardware architecture to a
 ccelerate BNNs inferred through Monte Carlo Dropout with high hardware per
 formance.\nWith the partial Bayesian inference applied, an automatic frame
 work is also proposed,\nwhich explores the trade-off between hardware and 
 algorithmi...\n\n\nTopic: Design\n\nKeyword: AI/ML System Design\n\nVirtua
 l Program: Presented In-Person
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