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BEGIN:VEVENT
DTSTAMP:20211208T164413Z
LOCATION:3014
DTSTART;TZID=America/Los_Angeles:20211209T113000
DTEND;TZID=America/Los_Angeles:20211209T120000
UID:dac_DAC 2021_sess159_RESEARCH244@linklings.com
SUMMARY:High-Performance FPGA-based Accelerator for Bayesian Neural Networ
 ks
DESCRIPTION:Research Manuscript\n\nHigh-Performance FPGA-based Accelerator
  for Bayesian Neural Networks\n\nFerianc\n\nIn this work, we propose a nov
 el FPGA-based hardware architecture to accelerate BNNs inferred through Mo
 nte Carlo Dropout with high hardware performance.\nWith the partial Bayesi
 an inference applied, an automatic framework is also proposed,\nwhich expl
 ores the trade-off between hardware and algorithmic performance.\nOur expe
 riments demonstrate that our hardware design can beat other state-of-the-a
 rt BNN accelerator,\nand our proposed automatic framework can effective fi
 nd the optimal points in the design space.\n\nTopic: Design\n\nKeyword: AI
 /ML System Design\n\nVirtual Program: Presented In-Person
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