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DTSTAMP:20211208T164413Z
LOCATION:3020
DTSTART;TZID=America/Los_Angeles:20211209T110000
DTEND;TZID=America/Los_Angeles:20211209T113000
UID:dac_DAC 2021_sess168_RESSP124@linklings.com
SUMMARY:Accelerating PCB Layout Editor using modern GPU architecture for c
 omplex designs
DESCRIPTION:Special Session (Research Track)\n\nAccelerating PCB Layout Ed
 itor using modern GPU architecture for complex designs\n\nKhailany, Pan, B
 ernard, Kryukov\n\nAs the complexity of modern electronics continuously gr
 ows, EDA products are getting challenged to keep up with performance. The 
 traditional CPU rendering approach is not going to be sufficient to be abl
 e to process 10s and 100s of millions of objects at a reasonable speed. Us
 ers are demanding a responsive tool running on modern hardware platforms. 
  This talk describes the approach of using GPUs to accelerate Cadence Alle
 gro rendering, augmenting the accuracy and quality of the graphics and imp
 roving other highly expensive tool functions.  With millions of objects to
  be rendered and manipulated in Allegro, we will discuss the following opt
 imizations that needed to be considered:  (1) How to efficiently render di
 fferent database element types; (2) Scene graph and memory cache, and why 
 they are a fit for the GPU;  (3) Incremental database updates; (4) Technol
 ogy that scales with the hardware used; and (5) the NVIDIA Path rendering 
 extension.\n\nTopic: EDA, Machine Learning/AI\n\nVirtual Program: Hosted i
 n Virtual Platform, Presented In-Person
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