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BEGIN:VEVENT
DTSTAMP:20211208T164507Z
LOCATION:2008
DTSTART;TZID=America/Los_Angeles:20211208T103000
DTEND;TZID=America/Los_Angeles:20211208T113000
UID:dac_DAC 2021_sess181@linklings.com
SUMMARY:Tune in to the Clocks!
DESCRIPTION:Designer, IP and Embedded Systems Track Presentations\n\nClock
  design continues to be an important aspect of the overall chip design. In
  this session, you would come across some novel techniques used to resolve
  challenges in clock design during chip development.\n\nClocking Methods w
 ith Focus on PCIe Gen4\n\nFong\n\nGood clock latency and skew can be hard 
 to attain on complex IP when using default settings. Difficulties during c
 lock build with PCIe Gen4 with a certain vendor has been strenuous and tim
 e-consuming. In this design, the clock and design are overly complex with 
 multiple IP configurations and over 36...\n\n---------------------\nECO pa
 tch generation & stitching to facilitate concurrent ECOs in High Performan
 ce Processor Designs\n\nEarl\n\nAs design sizes increase, the number of la
 st minute changes(ECO) and the time required to process them(TAT) also inc
 rease. During the fag end of the design cycle owing to the congestion a sm
 all change can lead to massive impact in terms of timing & routing resourc
 es & can greatly hamper chip schedul...\n\n---------------------\nUsing Cl
 ock Skew to Fix Hold: A Path-Depth Based Useful-Skew Approach to Reduce Ho
 ld Buffer Insertion\n\nGerstner\n\nModern clock tree synthesis (CTS) algor
 ithms take advantage of useful skew to improve setup time performance by i
 ncreasing the insertion delay to the capture flop on a setup-critical path
 . This improves setup total-negative slack at the cost of additional buffe
 ring on the clock network. However, the...\n\n\nTopic: Back-End Design\n\n
 Virtual Program: Presented In-Person
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