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DTSTART:19700308T020000
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BEGIN:VEVENT
DTSTAMP:20211208T164409Z
LOCATION:2008
DTSTART;TZID=America/Los_Angeles:20211208T103000
DTEND;TZID=America/Los_Angeles:20211208T105000
UID:dac_DAC 2021_sess181_des169@linklings.com
SUMMARY:Using Clock Skew to Fix Hold: A Path-Depth Based Useful-Skew Appro
 ach to Reduce Hold Buffer Insertion
DESCRIPTION:Designer, IP and Embedded Systems Track Presentations\n\nUsing
  Clock Skew to Fix Hold: A Path-Depth Based Useful-Skew Approach to Reduce
  Hold Buffer Insertion\n\nGerstner\n\nModern clock tree synthesis (CTS) al
 gorithms take advantage of useful skew to improve setup time performance b
 y increasing the insertion delay to the capture flop on a setup-critical p
 ath. This improves setup total-negative slack at the cost of additional bu
 ffering on the clock network. However, these useful skew CTS engines do no
 t simultaneously skew to minimize hold negative slack; hold is fixed in th
 e conventional manner of adding delay buffers at the last stage of the des
 ign flow, when area for these buffers is scarce. This presentation will il
 lustrate a novel approach whereby an exhaustive path depth analysis is per
 formed on a post-routed netlist to identify launching flops with little fu
 nctional (non-buffer) logic on their transitive fanout, but with a large n
 umber of hold buffers in this same fanout. Based on the post-signoff clock
  arrival times at these launch/capture flops, positive skew adjustments ar
 e computed for the target launching flops. By re-running the CTS and routi
 ng portions of the backend flow with these increased latency targets on ho
 ld-critical flops, the hold buffer count can be reduced. Using a commercia
 l physical implementation flow, IP processor core, and cell library, resul
 ts show a reduction in hold buffer count of up to 35%.\n\nTopic: Back-End 
 Design\n\nVirtual Program: Presented In-Person
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