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DTSTART:19700308T020000
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BEGIN:VEVENT
DTSTAMP:20211208T164409Z
LOCATION:2008
DTSTART;TZID=America/Los_Angeles:20211208T111000
DTEND;TZID=America/Los_Angeles:20211208T113000
UID:dac_DAC 2021_sess181_des208@linklings.com
SUMMARY:ECO patch generation & stitching to facilitate concurrent ECOs in 
 High Performance Processor Designs
DESCRIPTION:Designer, IP and Embedded Systems Track Presentations\n\nECO p
 atch generation & stitching to facilitate concurrent ECOs in High Performa
 nce Processor Designs\n\nEarl\n\nAs design sizes increase, the number of l
 ast minute changes(ECO) and the time required to process them(TAT) also in
 crease. During the fag end of the design cycle owing to the congestion a s
 mall change can lead to massive impact in terms of timing & routing resour
 ces & can greatly hamper chip schedules. So, when multiple last minute cha
 nges arrive it is necessary to categorize must haves, good to haves & dete
 rmine the implementable ones & apply the ECO change. As multiple ECOs arri
 ve over a period it becomes TAT inefficient to apply ECOs sequentially for
  evaluation & ECO application. So, there is a need for a methodology to fa
 cilitate concurrent processing of individual ECOs to determine ECO accepta
 bility & an ability to merge accepted ECO changes. This presentation descr
 ibes a tool (mdiff) and a methodology (ECO stitching) to allow unrelated E
 COs on a design to be implemented in parallel on copies of the design and 
 then applied to single copy for reduced TAT.\n\nTopic: Back-End Design\n\n
 Virtual Program: Presented In-Person
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