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DTSTART:19700308T020000
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BEGIN:VEVENT
DTSTAMP:20211208T164409Z
LOCATION:2008
DTSTART;TZID=America/Los_Angeles:20211208T105000
DTEND;TZID=America/Los_Angeles:20211208T111000
UID:dac_DAC 2021_sess181_des254@linklings.com
SUMMARY:Clocking Methods with Focus on PCIe Gen4
DESCRIPTION:Designer, IP and Embedded Systems Track Presentations\n\nClock
 ing Methods with Focus on PCIe Gen4\n\nFong\n\nGood clock latency and skew
  can be hard to attain on complex IP when using default settings. Difficul
 ties during clock build with PCIe Gen4 with a certain vendor has been stre
 nuous and time-consuming. In this design, the clock and design are overly 
 complex with multiple IP configurations and over 36 clocks. The four metho
 ds developed are regioning PCIe logic, analyzing the skew groups, insertin
 g a h-tree, and refraining certain clocks to be balanced. The methods impr
 oved turnaround time, clock skew, and clock latency; therefore, attaining 
 an acceptable clock tree in a reasonable time frame and enabling successfu
 l tapeouts on multiple projects.\n\nTopic: Back-End Design\n\nVirtual Prog
 ram: Presented In-Person
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