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DTSTAMP:20211208T164510Z
LOCATION:2008
DTSTART;TZID=America/Los_Angeles:20211206T133000
DTEND;TZID=America/Los_Angeles:20211206T143000
UID:dac_DAC 2021_sess182@linklings.com
SUMMARY:All Routes Lead to Closing Timing
DESCRIPTION:Designer, IP and Embedded Systems Track Presentations\n\nTimin
 g closure is the final stage of physical implementation, and where some of
  the most complex challenges can be encountered, creating critical schedul
 e risk.  This session covers methods to help ease timing closure, includin
 g optimization of routing layer usage, removal of pessimism from margins, 
 quick/accurate parametrized block placement, and accelerated hierarchical 
 ECO generation.\n\nAging Timing Analysis Based on EMPYREAN-XTime\n\nShey\n
 \nReliability of integrated circuits is getting growing concern in modern 
 semiconductor industry. However, standard cells in advanced FinFET technol
 ogy are also increasingly sensitive to aging effects. Timing degradation c
 aused by these aging effects during signal propagated in paths will direct
 ly aff...\n\n---------------------\nRouting layer re-optimization in Physi
 cal Synthesis\n\nReddy\n\nPhysical Synthesis tools typically use heuristic
  optimization techniques to cope with ever increasing design sizes. They a
 lso need to deal with optimizing multiple objectives such as improving tim
 ing, decreasing area/power, reducing congestion, and so on. In addition, t
 he accuracy of optimization en...\n\n---------------------\nMethodology fo
 r early timing and floorplanning closure in custom circuit design\n\nRamam
 urthy\n\nA pre-layout methodology is disclosed that allows designers to ac
 hieve a high degree of timing and floorplanning closure during the early s
 tages of custom macro circuit design.  The methodology utilizes Electronic
  Design Automation (EDA) tools that facilitate an efficient, iterative pro
 cess of floor...\n\n\nTopic: Back-End Design\n\nVirtual Program: Presented
  In-Person
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