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BEGIN:VEVENT
DTSTAMP:20211208T164405Z
LOCATION:2008
DTSTART;TZID=America/Los_Angeles:20211206T141000
DTEND;TZID=America/Los_Angeles:20211206T143000
UID:dac_DAC 2021_sess182_des149@linklings.com
SUMMARY:Aging Timing Analysis Based on EMPYREAN-XTime
DESCRIPTION:Designer, IP and Embedded Systems Track Presentations\n\nAging
  Timing Analysis Based on EMPYREAN-XTime\n\nShey\n\nReliability of integra
 ted circuits is getting growing concern in modern semiconductor industry. 
 However, standard cells in advanced FinFET technology are also increasingl
 y sensitive to aging effects. Timing degradation caused by these aging eff
 ects during signal propagated in paths will directly affect the operating 
 frequency and even lead to timing issues, reducing the reliability and lif
 e-time of the integrated circuits. In this case, Path-based aging timing s
 imulation is of paramount importance to eliminate such timing risks and to
  ensure the circuits reliability.\nHere, We will share our practice of usi
 ng EMPYREAN-XTime to perform path-level aging timing simulations as follow
 s:\n1. Applying spice simulation to check the timing information after agi
 ng, from which we achieve true critical path verification, timing degradat
 ion measurement and accurate timing under various aging conditions.\n2. Es
 tablishing a machine learning based predictor to speed up the aging timing
  analysis. The predictor can figure out the delay of 2000 paths within 60 
 s, with the normalized root mean square error of the overall prediction re
 sults less than 0.2%.\n\nTopic: Back-End Design\n\nVirtual Program: Presen
 ted In-Person
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