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DTSTART:19700308T020000
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BEGIN:VEVENT
DTSTAMP:20211208T164405Z
LOCATION:2008
DTSTART;TZID=America/Los_Angeles:20211206T133000
DTEND;TZID=America/Los_Angeles:20211206T135000
UID:dac_DAC 2021_sess182_des167@linklings.com
SUMMARY:Methodology for early timing and floorplanning closure in custom c
 ircuit design
DESCRIPTION:Designer, IP and Embedded Systems Track Presentations\n\nMetho
 dology for early timing and floorplanning closure in custom circuit design
 \n\nRamamurthy\n\nA pre-layout methodology is disclosed that allows design
 ers to achieve a high degree of timing and floorplanning closure during th
 e early stages of custom macro circuit design.  The methodology utilizes E
 lectronic Design Automation (EDA) tools that facilitate an efficient, iter
 ative process of floorplanning a macro using Placement by Instance Paramet
 er (PIP) and generating an accurate Steiner estimated parasitic (STEP) RC 
 netlist.  This parasitic netlist is used to provide an early and accurate 
 indication of macro performance and timing margins.  Case studies reveal p
 re- and post-layout timing as well as macro dimension to fall typically wi
 thin 10%, thus giving high confidence of timing and floorplanning closure 
 early in the design cycle.\n\nTopic: Back-End Design\n\nVirtual Program: P
 resented In-Person
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