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DTSTART:19700308T020000
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BEGIN:VEVENT
DTSTAMP:20211208T164405Z
LOCATION:2008
DTSTART;TZID=America/Los_Angeles:20211206T135000
DTEND;TZID=America/Los_Angeles:20211206T141000
UID:dac_DAC 2021_sess182_des240@linklings.com
SUMMARY:Routing layer re-optimization in Physical Synthesis
DESCRIPTION:Designer, IP and Embedded Systems Track Presentations\n\nRouti
 ng layer re-optimization in Physical Synthesis\n\nReddy\n\nPhysical Synthe
 sis tools typically use heuristic optimization techniques to cope with eve
 r increasing design sizes. They also need to deal with optimizing multiple
  objectives such as improving timing, decreasing area/power, reducing cong
 estion, and so on. In addition, the accuracy of optimization environment v
 aries as we go through the Physical Synthesis flow. All these factors may 
 lead to sub-optimal thick metal layer assignments and inferior timing QOR 
 on some timing critical nets. We propose a novel routing layer re-optimiza
 tion technique that attempts to (re)assign thick metal routing resource wi
 th the goal of significantly mitigating routing congestion as well as impr
 oving design timing QOR.\nThe proposed technique starts with an aggressive
  layer demotion (during late timing optimization stages) in the routing co
 ngested regions even at the expense of timing QOR to provide an opportunit
 y to correct/improve layer assignment. The timing QOR recovery/improvement
  phase follows next, initially with cheaper optimizations to reduce the ne
 ed for precious routing layer resource as well as to correct any underlyin
 g issues such as sub-optimal locations / weak power levels. Next, we perfo
 rm a gradual & controlled layer reassignment / buffering in a congestion-a
 ware environment to mitigate congestion increases while improving timing Q
 OR.\n\nTopic: Back-End Design\n\nVirtual Program: Presented In-Person
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