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DTSTART:19700308T020000
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BEGIN:VEVENT
DTSTAMP:20211208T164407Z
LOCATION:2008
DTSTART;TZID=America/Los_Angeles:20211207T140000
DTEND;TZID=America/Los_Angeles:20211207T143000
UID:dac_DAC 2021_sess186_IP117@linklings.com
SUMMARY:Smart digital sensors against tampering
DESCRIPTION:Designer, IP and Embedded Systems Track Presentations\n\nSmart
  digital sensors against tampering\n\nGuilley\n\nConnected chips in portab
 le devices shall both be safe and secure.\nTherefore, they must be endowed
  with specific hardware to detect hazards and attacks.\nIndustry recognize
 d standards specify requirements in this respect: IEC 61508, ISO 26262 reg
 arding functional safety, and FIPS 140 version 3 regarding cyber-security.
 \n\nAt the same time, chips at end-point (CPS, IoT, M2M, automotive, etc.)
  face challenging constraints, especially low of cost and low time-to-mark
 et.\n\nThis presentation highlights an integrated sensor, amenable to bein
 g deployed within chips in several copies interleaved with the design it d
 etects faults in.\nThe three main innovations of this sensor are:\ni) a fr
 ont-end integration (owing to sensor being implemented in standard cells),
 \nii) a wide range of abnormality detections (temperature, voltage, glitch
 es, etc.) and\niii) a low false positive rate made possible by a machine l
 earning analysis of several sensors to make one accurate decision.\n\nThe 
 machine learning part is integrated (50 kGE for 16 sensors) in logic, and 
 detects the faults in 1000 clock cycles.\nIn addition, the ML engine is ab
 le to classify the issue: attack vs hazard, and nature of "glitch" (electr
 omagnetic, clock, etc.)\n\nTopic: IP\n\nVirtual Program: Presented In-Pers
 on
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