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BEGIN:VEVENT
DTSTAMP:20211208T164404Z
LOCATION:2010/2012
DTSTART;TZID=America/Los_Angeles:20211206T111000
DTEND;TZID=America/Los_Angeles:20211206T113000
UID:dac_DAC 2021_sess187_ESS112@linklings.com
SUMMARY:SoC Architectural Exploration for AI and ML accelerators with RISC
 -V
DESCRIPTION:Designer, IP and Embedded Systems Track Presentations\n\nSoC A
 rchitectural Exploration for AI and ML accelerators with RISC-V\n\nHsu\n\n
 SoC developers and system designers are looking at hardware acceleration o
 ptions for AI and Machine Learning applications moving from cloud-based al
 gorithms to dedicated hardware. Since the algorithms are already configure
 d for multicore support the tradeoffs become focused on the structure of p
 rocessor arrays and the optimum performance requirements at each node. In 
 addition to the flexibility offered by the open standard ISA of RISC-V to 
 configure the core features to match the compute requirement, RISC-V offer
 s the options to add custom extensions and instructions that allows a grea
 ter degree of system optimization. New extensions can be targeted at the a
 pplication workload or as dedicated communication channels between the cor
 es, nodes and/or interfaces to the NoC.  \nThis talk covers a methodology 
 to evaluate the hardware options by enabling early system architectural ex
 ploration using software to uncover the optimum design configurations.\n\n
 Topic: Embedded Systems\n\nVirtual Program: Presented In-Person
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