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DTSTAMP:20211208T164511Z
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DTSTART;TZID=America/Los_Angeles:20211206T133000
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UID:dac_DAC 2021_sess196_TUT104@linklings.com
SUMMARY:Approximate Synthesis: State-of-the-art and Future Directions
DESCRIPTION:Tutorial\n\nApproximate Synthesis: State-of-the-art and Future
Directions\n\nPozzi, Reda, Reda, Roy, Scarabottolo...\n\nApproximate comp
uting is an emerging paradigm that enables reduced design area and power c
onsumption by relaxing the requirement for full accuracy. This paradigm is
particularly attractive in applications where the underlying computation
has inherent resilience to small errors, which include, among many others,
machine learning, computer vision and signal processing. In circuit desig
n, a major challenge is the capability to synthesize approximate circuits
automatically, without manually relying on the expertise of designers. In
this tutorial, we will (1) overview error metrics and error estimation met
hods, (2) overview all major methods devised to synthesize approximate cir
cuits given their exact functionality, (3) provide video tutorials for ava
ilable open-source approximate synthesis tools, and (4) discuss future pro
spects of approximate logic synthesis.\n\nWe will outline the importance o
f a preliminary error-modeling phase aimed at guiding Approximate Logic Sy
nthesis (ALS) algorithms towards efficient solutions. We will discuss the
state of the art approaches for error-modeling, along with their strengths
and weaknesses. Available design and benchmark circuits will be overviewe
d together with their associated quality metrics.\n\nFor Approximate Logic
Synthesis, we will provide a categorization of existing techniques illust
rating the differences between netlist transformation, where a netlist is
manipulated by modifying its structure, and Boolean rewriting, whereby the
logic of the circuit is first captured in a formal Boolean representatio
n that is modified to yield an approximate Boolean representation; this is
, in turn, synthesized to a gate-based netlist. For the first category, we
review four different techniques: (i) greedy heuristics for netlist pruni
ng (ii) greedy heuristics for netlist manipulation (iii) stochastic netlis
t transformation; and (iv) exhaustive exploration for netlist pruning. For
Boolean rewriting instead, we review the following techniques: (i) logic
rewriting by Boolean optimization; (ii) logic rewriting by Boolean matrix
factorization; (iii) logic rewriting by binary decision diagrams; and (iv)
logic rewriting by and-inverter graphs. We will provide a quantitative co
mparison of the performance of some of existing ALS techniques.\n\nApproxi
mate High-Level Logic Synthesis (AHLS) focuses on the highest level of abs
traction for ALS, where the function is described at behavioural level, su
ch as in RTL Verilog or C language. We overview AHLS techniques that (i) i
dentify acceptable reductions to numerical precisions, (ii) simplify arith
metic expressions, (ii) deploy approximate arithmetic instead of exact ari
thmetic units, and (iii) utilize mixed-precision loop control and loop per
foration. We will show how machine learning methods based on genetic prog
ramming can be used to approximate gate- and RT-level circuits. As many ca
ndidate approximate circuits are automatically generated by these methods,
it is essential to quickly evaluate these circuits in terms of approximat
ion error and electrical parameters. State of the art methods effectively
combining search algorithms and error evaluation will be discussed. \n\nWe
will also provide an overview and video demos of existing open-source too
ls for approximate synthesis. In particular, we will overview (i) the BACS
benchmark set, (ii) ABACUS, which is a tool for AHLS, (iii) BLASYS, whic
h is a tool for ALS; (iv) Partition and Propagate, which is a tool for err
or estimation;\n\nVirtual Program: Presented In-Person
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